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3909925 : N-Channel charge coupled device fabrication process
INVENTORS: Forbes; Leonard, Fayetteville, AR
Yeargan; Jerry R., Fayetteville, AR
ASSIGNEES: Telex Computer Products, Inc., Tulsa, OK
ISSUED:Oct. 7 , 1975 FILED: May 6 , 1974
SERIAL NUMBER: 467055 MAINT. STATUS:
INTL. CLASS (Ed. 2): B01J 17/00;
U.S. CLASS:029-578; 029-589; 029-591; 357-024;
FIELD OF SEARCH: 029-571,577,578,589,580,591 ; 357-024 ;
AGENTS:none

ABSTRACT:   This abstract describes a process of construction of an N-channel charge coupled device. It provides a step-by-step series of operations which will produce on a P-type substrate of silicon a series of interposed spaced polysilicon gates and aluminum gates. The polysilicon gates are deposited on a thin silicon nitrade layer which is positioned on a thin silicon oxide layer, both of minimum thickness, so there is good capacitive coupling between the polysilicon and the silicon. A thick layer of silicon oxide is formed over the polysilicon gate, after which the nitride layer between the polysilicon gates is etched away. A silicon oxide layer is deposited in the space between the nitride areas and on top of that an aluminum gate is deposited. Conventional means are provided to attach conductor leads to the polysilicon gates. If desired Boron or other elements can be implanted in the silicon before the oxide and aluminum gates are deposited.

U.S. REFERENCES:   Show the 9 patents that reference this one
Patent No. Inventor Issued Title
3676715 Brojdo7 /1972 SEMICONDUCTOR APPARATUS FOR IMAGE SENSING AND DYNAMIC STORAGE
3770988 Engeler11 /1973 SELF-REGISTERED SURFACE CHARGE LAUNCH-RECEIVE DEVICE AND METHOD FOR MAKING
3796928 Doo3 /1974 SEMICONDUCTOR SHIFT REGISTER
3845295 Williams10 /1974 CHARGE-COUPLED RADIATION SENSING CIRCUIT WITH CHARGE SKIM-OFF AND RESET

EXEMPLARY CLAIM(s): Show all 9 claims

    What is claimed is:
    • 1. In the process of making a semi-conductor charge coupled device in which a metal transfer gate is positioned in the space between two spaced-apart silicon storage gates, the improvement comprising the steps of
      • a. preparing a chip of silicon semi-conductor;
      • b. forming a thin continuous first layer of silicon dioxide on top of said chip;
      • c. forming a thin continuous second layer of silicon nitride on top of said first layer;
      • d. forming a thick layer of polycrystalline silicon (polysilicon) on top of said second layer, said third layer being etched in the shape of spaced rectangular areas of selected size and spacing;
      • e. forming a thick fourth layer of silicon dioxide completely covering all exposed areas of said third layer;
      • f. etching away said second silicon nitride layer between said areas of silicon dioxide coated polysilicon;
      • g. forming a thin fifth layer of silicon oxide over said areas of silicon dioxide coated polysilicon and over the space between said areas;
      • h. depositing a sixth metal layer over said fifth layer in the space between said spaced apart areas of said fourth layer; and
      • i. providing conductor means to contact said areas of said third layer.

    RELATED U.S. APPLICATIONS: none

    FOREIGN APPLICATION PRIORITY DATA: none
    FOREIGN REFERENCES: none
    OTHER REFERENCES: none
    PRIMARY/ASSISTANT EXAMINERS: Tupman; W.;
    ADDED TO DATABASE: Aug. 21, 1996


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