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4992840 : Carbon doping MOSFET substrate to suppress hot electron trapping
INVENTORS: Haddad; Homayoon, Corvallis, OR
Forbes; Leonard, Corvallis, OR
Richling; Wayne P., Corvallis, OR
ASSIGNEES: Hewlett-Packard Company, Palo Alto, CA
ISSUED:Feb. 12, 1991 FILED: Sep. 21, 1989
SERIAL NUMBER: 412067 MAINT. STATUS:
INTL. CLASS (Ed. 5): H01L 29/78; H01L 29/10; H01L 29/06;
U.S. CLASS:357-023.15; 357-023.3; 357-023.9; 357-023.12;
FIELD OF SEARCH: 357-23.15,23.3,23.12,23.8,23.13,23.11,23.4,23.9 ;
AGENTS:none

ABSTRACT:   A MOSFET device having a near-micrometer or submicrometer channel length and designed to operated under conditions that cause generation of hot carriers is carbon doped in the silicon substrate at the gate oxide-silicon interface. The oxide-silicon interface can include hydrogen atoms. These atoms are mostly bonded to carbon atoms, more strongly than hydrogen bonds to silicon, so that hot carriers are less likely to dissociate the hydrogen atoms and form hot carrier trapping sites at the interface. Hot carrier aging is thus substantially reduced. This capability is particularly useful in submicrometer devices, avoiding need to reduce normal operating voltages.

U.S. REFERENCES:   Show the 5 patents that reference this one
Patent No. Inventor Issued Title
4636834 Shepard1 /1987 Submicron FET structure and method of making

EXEMPLARY CLAIM(s): Show all 13 claims

    We claim:
    • 1. In an integrated circuit, a hot-electron aging-resistant metal-oxide-silicon field effect transistor (MOSFET) comprising:
      • a silicon substrate having an upper substrate surface;
      • a gate oxide layer covering a first portion of the substrate and forming an oxide-silicon interface at the substrate surface;
      • a conductive gate contact overlying the gate oxide;
      • a conductive source contact covering a second portion of the substrate on one side of the gate oxide layer;
      • a conductive drain contact covering a third portion of the substrate on an opposite side of the gate oxide layer;
      • a channel diffusion of dopant impurities in the first portion of the substrate under the gate oxide defining a threshold voltage of the transistor;
      • source and drain diffusions of dopant impurities in the second and third portions of the substrate, respectively;
      • the source and drain diffusions being spaced so that field strength in the drain is at least 105 volts per centimeter such that hot carriers are generated in the first portion of the silicon substrate; and
      • the first portion of the silicon substrate being doped with carbon atoms in a concentration of at least 1E16/cm3 at the interface so that trapping of the hot carriers at the interface is suppressed and a shift in the threshold voltage over time is minimized.

    RELATED U.S. APPLICATIONS: none

    FOREIGN APPLICATION PRIORITY DATA: none

    FOREIGN REFERENCES:
    Document No.CountryDateIntl. Class
    56-125846 Japan3 /1980  

    OTHER REFERENCES:

    • Sze, S. M., Semiconductor Devices Physics and Technology, 1985, pp. 318-319.
    • Chen, et al., "Suppression of Hot-Carrier Effects in Submicrometer CMOS Technology", IEEE Trans. on Elec. Dev., vol. 35, No. 12, pp. 2210-2219 (Dec. 1988).
    PRIMARY/ASSISTANT EXAMINERS: Hille; Rolf; Potter; Roy K.
    ADDED TO DATABASE: Aug. 23, 1996
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