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United States Patent 5,666,306
Forbes Sept. 9, 1997

Multiplication of storage capacitance in memory cells by using the Miller effect
Inventors: Forbes; Leonard (Corvallis, OR).
Assignee: Micron Technology, Inc. (Boise, ID).
Appl. No.: 706,662
Filed: Sept. 6, 1996
Intl. Cl. : G11C 7/00
Current U.S. Cl.: 365/149; 365/203
Field of Search: 365/149, 203

References Cited | [Referenced By]

U.S. Patent Documents
4,970,689Nov., 1990Kenney 365/189.01
4,999,811Mar., 1991Banerjee 365/149
5,066,607Nov., 1991Banerjee 437/52
5,220,530Jun., 1993Itoh 365/189.01
5,375,086Dec., 1994Wahlstrom 365/149
5,414,656May, 1995Kenney 365/149
5,416,371May, 1995Katayama et al. 365/149
5,448,513Sept., 1995Hu et al. 365/150
5,517,445May, 1996Imai et al. 365/149 X
5,579,257Nov., 1996Tai 365/149

Other References

P. Cottrell, et al., "N-Well Design for Trench DRAM Arrays", IEEE, Abstract of Int. Electron Device Meeting, pp. 584-587, (1988).

T. Ema, et al., "3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMs", IEDM, Abstract of Int. Electron Device Meeting, pp. 592-595, (1988).

J. P. Mize, et al., "Semiconductor Memory Design and Applications", McGraw-Hill New York, pp. 115-138, (1973).


Primary Examiner: Dinh; Son T.
Attorney, Agent or Firm: Schwegman, Lundberg, Woessner & Kluth, P.A.

Abstract

A memory cell for a dynamic random access memory includes a storage transistor that is connected for operation as an amplifier, the drain-to-gate capacitance of the storage transistor functioning as the storage capacitance for the memory cell. An access transistor is interposed between a bit line and the input of the amplifier, for coupling the amplifier to the bit line during write and read operations for the memory cell. During memory cell read operations, the storage capacitance is effectively multiplied by 1+Av, where Av is the gain of the amplifier, providing Miller-effect amplification of the storage capacitance.

18 Claims, 5 Drawing Figures

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