United States Patent 5,691,230

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United States Patent	5,691,230
Forbes	Nov. 25, 1997

Technique for producing small islands of silicon on insulator

Inventors:	Forbes; Leonard (Corvallis, OR).
Assignee:	*Micron* *Technology*, Inc. (Boise, ID).
Appl. No.:	706,230
Filed:	Sept. 4, 1996

Intl. Cl. :	H01L 21/76
Current U.S. Cl.:	437/62; 148/DIG 50; 437/61; 437/67; 437/72
Field of Search:	437/61, 62, 67, 72, 73; 148/DIG. 50

References Cited | [Referenced By]

U.S. Patent Documents

4,437,226	Mar., 1984	Soclof	437/67
4,561,932	Dec., 1985	Gris et al.	437/67
4,580,331	Apr., 1986	Soclof	437/61
4,604,162	Aug., 1986	Sobczak	156/657
4,615,746	Oct., 1986	Kawakita et al.	437/72
5,391,911	Feb., 1995	Beyer et al.	257/522
5,466,625	Nov., 1995	Hsieh et al.	437/52
5,528,062	Jun., 1996	Hsieh et al.	257/298

Primary Examiner: Dang; Trung
Attorney, Agent or Firm: Schwegman, Lundberg, Woessner & Kluth, P.A.

Abstract

Using sub-micron technology, silicon on insulator (SOI) rows and islands are formed in a silicon substrate. Trenches are directionally-etched in the silicon substrate, leaving rows of silicon between the trenches. Silicon nitride is then deposited over the trenches, extending partly down the sides of the trenches. An isotropic chemical etch is then used to partially undercut narrow rows of silicon in the substrate. A subsequent oxidation step fully undercuts the rows of silicon, isolating the silicon rows from adjacent active areas. Devices, such as transistors for CMOS and DRAMs, are then formed in active areas, wherein the active areas are defined on the silicon rows by LOCal Oxidation of Silicon (LOCOS).

10 Claims, 7 Drawing Figures

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