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|United States Patent||5,835,403|
|Forbes||Nov. 10, 1998|
A memory cell for a dynamic random access memory includes a storage transistor that is connected for operation as an amplifier, the drain-to-gate capacitance of the storage transistor functioning as the storage capacitance for the memory cell. An access transistor is interposed between a bit line and the input of the amplifier, for coupling the amplifier to the bit line during write and read operations for the memory cell. During memory cell read operations, the storage capacitance is effectively multiplied by 1+Av, where Av is the gain of the amplifier, providing Miller-effect amplification of the storage capacitance.
|Inventors:||Forbes; Leonard (Corvallis, OR).|
|Assignee:||Micron Technology, Inc. (Boise, ID).|
|Filed:||Jun. 20, 1997|
|Continuation of (including streamline cont.) Ser. No. 706,662, Sept. 6, 1996, Pat. No. 5,666,306.|
|Intl. Cl. :||G11C 11/24|
|Current U.S. Cl.:||365/149; 365/203|
|Field of Search:||365/149, 203|
|5,448,513||Sept., 1995||Hu et al.||365/150|
|5,483,482||Jan., 1996||Yamada et al.||365/149|
Cottrell, P., et al., "N-Well Design for Trench DRAM Arrays", IEEE, Abstract of Int. Electron Device Meeting, pp. 584-587, (1988).
Ema, T., et al., "3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMs", IEDM, Abstract of Int. Electron Device Meeting, pp. 592-595, (1988).
Mize, J.P., et al., "Semiconductor Memory Design and Applications", McGraw-Hill New York, pp. 115-138, (1973).
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