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| United States Patent | 5,879,996 |
| Forbes | Mar. 9, 1999 |
Abstract
A PMOS transistor is formed in a CMOS integrated circuit, having a Si(1-x) Ge(x) /Si heterojunction between the channel region and the substrate. The method is applicable to large volume CMOS IC fabrication. Germanium is implanted into a silicon substrate, through a gate oxide layer. The substrate is then annealed in a low temperature furnace, to form Si(1-x) Ge(x) in the channel region.
| Inventors: | Forbes; Leonard (Corvallis, OR). |
| Assignee: | Micron Technology, Inc. (Boise, ID). |
| Appl. No.: | 717,198 |
| Filed: | Sept. 18, 1996 |
| Intl. Cl. : | H01L 21/336 |
| Current U.S. Cl.: | 438/289; 438/299; 438/528 |
| Field of Search: | 438/289, 290, 291, 299, 301, 305, 306, 307, 528, 158 |
| 4,394,181 | Jul., 1983 | Nicholas | 438/298 |
| 5,145,794 | Sept., 1992 | Kase et al. | 438/515 |
| 5,254,484 | Oct., 1993 | Hefner et al. | 438/373 |
| 5,298,435 | Mar., 1994 | Aronowitz et al. | 438/535 |
| 5,312,766 | May, 1994 | Aronowitz et al. | 438/291 |
| 5,426,069 | Jun., 1995 | Selvakumar et al. | 438/60 |
| 4-34942 | Feb., 1992 | JP | 438/158 |
M. Berti, et al., "Composition and Structure of Si-Ge Layers Produced by Ion Implantation and Laser Melting", J. Mater. Res., vol. 6, No. 10, pp. 2120-2126, Oct. (1991).
M. Berti, et al., "Laser Induced Epitaxial Regrowth of Si(1-x) Ge(x) /Si Layers Produced by Ge Ion Implantation", Appl. Surf. Sci. vol. 43, pp. 158-164, Jan. (1989).
B. T. Chilton, et al., "Solid Phase Epitaxial Regrowth of Strained Si(1-x) Ge(x) /Si Strained-layer Structures Amorphized by Ion Implantation", Appl. Phys. Lett., vol. 54, No. 1, pp. 42-44, Jan. (1989).
Vandebroek, Bernard S. Myerson, et al., "SiGe-Channel Heterojunction p-MOSFET's", IEEE Trans. on Electron Devices, vol. 41, No. 1, pp. 90-100, (Jan. 1994).
D. C. Paine, et al., "The Growth of Strained Si(1-x) Ge(x) Alloys on (100) Silicon Using Solid Phase Epitaxy", J. Mater Re., vol. 5, No. 5, pp. 1023-1031, May (1990).
R. People, et al., "Calculation of critical layer thickness versus Lattice Mismatch for Si(1) -xGe(x) /Si Strained-layer Heterostructures", Appl. Phys. Lett., Aug. (1985), pp. 322-324, Erraltum.
G.A. Garcia et al, "High Quality CMOS in Thin (100nm) Silicon on Sapphire", IEEE Elect. Device Lett, vol. 9, No. 1, pp. 32-34, (Jan. 1988).
D. K. Nayak, K. L. Wang, et al., "High Performance GeSi Quantum-Well PMOS on SIMOX", Proc. Int. Electron Device Meeting, San Francisco, pp. 777-780, (Dec. 1992).
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