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Abstract

A gain memory cell formed by merged n-channel and p-channel field-effect transistors wherein the body portion of the p-channel transistor is coupled to the charge storage node of the memory cell for providing a bias to the body of the p-channel transistor that varies as a function of the data stored by the memory cell. The stored charge is sensed indirectly in that the stored charge modulates the conductivity of the p-channel transistor so that the p-channel transistor has a first turn-on threshold for a stored logic "1" condition and a second turn-on threshold for a stored logic "0" condition. Consequently, a small storage node capacitance can be used, reducing the overall volume of the cell. The gain memory cell has a single internal contact and only two lines are required for operation of the gain memory cell. The internal contact is formed along a sidewall of an isolation trench, minimizing the surface area of the memory cell.

Other References

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