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|United States Patent||5,897,351|
|Forbes||Apr. 27, 1999|
A gain memory cell formed by merged n-channel and p-channel field-effect transistors wherein the body portion of the p-channel transistor is coupled to the charge storage node of the memory cell for providing a bias to the body of the p-channel transistor that varies as a function of the data stored by the memory cell. The stored charge is sensed indirectly in that the stored charge modulates the conductivity of the p-channel transistor so that the p-channel transistor has a first turn-on threshold for a stored logic "1" condition and a second turn-on threshold for a stored logic "0" condition. Consequently, a small storage node capacitance can be used, reducing the overall volume of the cell. The gain memory cell has a single internal contact and only two lines are required for operation of the gain memory cell. The internal contact is formed along a sidewall of an isolation trench, minimizing the surface area of the memory cell.
|Inventors:||Forbes; Leonard (Corvallis, OR).|
|Assignee:||Micron Technology, Inc. (Boise, ID).|
|Filed:||Aug. 21, 1997|
|Division of Ser No. 804,179, Feb. 21, 1997, Pat. No. 5,732,014.|
|Intl. Cl. :||H01L 21/8242|
|Current U.S. Cl.:|
|Field of Search:||438/238-259, 381-399, 149, 311|
|5,122,986||Jun., 1992||Lim et al.||365/189.11|
|5,214,603||May, 1993||Dhong et al.|
|5,308,783||May, 1994||Krautschneider et al.||437/52|
|5,448,513||Sept., 1995||Hu et al.||365/150|
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