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United States Patent 5,897,351
Forbes Apr. 27, 1999

Method for forming merged transistor structure for gain memory cell


A gain memory cell formed by merged n-channel and p-channel field-effect transistors wherein the body portion of the p-channel transistor is coupled to the charge storage node of the memory cell for providing a bias to the body of the p-channel transistor that varies as a function of the data stored by the memory cell. The stored charge is sensed indirectly in that the stored charge modulates the conductivity of the p-channel transistor so that the p-channel transistor has a first turn-on threshold for a stored logic "1" condition and a second turn-on threshold for a stored logic "0" condition. Consequently, a small storage node capacitance can be used, reducing the overall volume of the cell. The gain memory cell has a single internal contact and only two lines are required for operation of the gain memory cell. The internal contact is formed along a sidewall of an isolation trench, minimizing the surface area of the memory cell.

Inventors: Forbes; Leonard (Corvallis, OR).
Assignee: Micron Technology, Inc. (Boise, ID).
Appl. No.: 916,933
Filed: Aug. 21, 1997

Related U.S. Application Data
Division of Ser No. 804,179, Feb. 21, 1997, Pat. No. 5,732,014.
Intl. Cl. : H01L 21/8242
Current U.S. Cl.:
Field of Search: 438/238-259, 381-399, 149, 311

References Cited | [Referenced By]

U.S. Patent Documents
4,970,689Nov., 1990Kenney 365/189.01
4,999,811Mar., 1991Banerjee 365/149
5,066,607Nov., 1991Banerjee 437/52
5,122,986Jun., 1992Lim et al. 365/189.11
5,134,083Jul., 1992Matthews
5,214,603May, 1993Dhong et al.
5,220,530Jun., 1993Itoh 365/189.01
5,308,783May, 1994Krautschneider et al. 437/52
5,448,513Sept., 1995Hu et al. 365/150

Other References

Cottrell, P., et al., "N-Well Design for Trench DRAM Arrays", IEEE, Abstract of Int. Electron Device Meeting, pp. 584-587, (1988).

Ema, T., et al., "3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMs", IEDM, Abstract of Int. Electron Device Meeting, pp. 592-595, (1988).

Kim, W., et al., "An Experimental High-Density DRAM Cell with a Built-in Gain Stage", IEEE Journal of Solid-State Circuits, vol. 29, No. 8, 978-981, (1994).

Krautschneider, F., et al., "Planar Gain Cell for Low Voltage Operation and Gigabit Memories", Symposium on VLSI Technology Digest of Technical Papers, 139-140, (1995).

Kuge, S., et al., "SOI-DRAM Circuit Technologies for Low Power High Speed Multigiga Scale Memories", IEEE Journal of Solid-State Circuits, 31, 586-591, (Apr., 1996).

Shukuri, S., et al., "A Complementary Gain Cell Technology for Sub-1V Supply DRAMs", Ext. Abs. of IEEE Int. Electron Device Meeting, 1006-1008, (1992).

Shukuri, S., et al., "A Semi-Static Complementary Gain Cell Technology for Sub-1 V Supply DRAMs", IEEE Transactions on Electron Devices, vol. 41, No. 6, 926-931, (Jun., 1994).

Shukuri, S., et al., "Super-Low Voltage Operation of a Semi-Static Complementary Gain DRAM Memory Cell", VLSI Tech. Symposium, 23-24, (1993).

Sunouchi, K., et al., "A Self Amplifying (SEA) Cell for Future High Density DRAMs", ULSI Research Center, Toshiba Corporation, 17.1.1-17.1.4, (1991).

Terauchi, M., et al., "A Surrounding Gate Transistor (SGT) Gain Cell for Ultra High Density DRAMs", VLSI Tech. Symposium, 21-22, (1993).

Wann, H., et al., "A Capacitorless DRAM Cell on SOI Substrate", Ext. Abs. IEEE Int. Electron Devices Meeting, 635-638, (1993).

Primary Examiner: Tsai; Jey
Attorney, Agent or Firm: Schwegman, Lundberg, Woessner & Kluth, P.A.
24 Claims, 14 Drawing Figures

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