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United States Patent 5,920,121
Forbes, et. al. Jul. 6, 1999

Methods and structures for gold interconnections in integrated circuits


A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with aluminum wires. Making the aluminum wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with aluminum to form the aluminum wires. Trench digging is time consuming and costly. Moreover, aluminum has higher electrical resistance than other metals, such as gold. Accordingly, the invention provides a new "self-trenching" or "self-planarizing" method of making coplanar gold wires. Specifically, one embodiment forms a first layer that includes silicon and germanium; oxidizes a region of the first layer to define an oxidized region and a non-oxidized region; and reacts gold with the non-oxidized region. The reaction substitutes, or replaces, the non-oxidized region with gold to form gold wires coplanar with the first layer. Another step removes germanium oxide from the oxidized region to form a porous insulation having a very low dielectric constant, thereby reducing capacitance. Thus, the present invention not only eliminates the timing-consuming, trench-digging step of conventional methods, but also reduces resistance and capacitance which, in turn, enable faster, more-efficient integrated circuits.

Inventors: Forbes; Leonard (Corvallis, OR); Farrar; Paul A. (So. Burlington, VT); Ahn; Kie Y. (Chappaqua, NY).
Assignee: Micron Technology, Inc. (Boise, ID).
Appl. No.: 30,188
Filed: Feb. 25, 1998
Intl. Cl. : H01L 23/48, H01L 23/52, H01L 29/40
Current U.S. Cl.: 257/742; 257/522; 257/743
Field of Search: 257/742, 616, 743, 744, 745, 276, 522

References Cited | [Referenced By]

U.S. Patent Documents
4,702,941Oct., 1987Mitchell et al. 427/250
4,959,705Sept., 1990Lemnious 257/522
5,148,260Sept., 1992Inoue et al. 257/276
5,187,560Feb., 1993Yoshida et al. 257/743
5,324,684Jun., 1994Kermani et al. 437/95
5,341,016Aug., 1994Prall et al. 257/412
5,371,035Dec., 1994Pfiester et al. 437/69
5,470,801Nov., 1995Kapoor et al. 437/238
5,510,645Apr., 1996Fitch et al. 257/522
5,563,448Oct., 1996Lee et al. 257/742
5,757,072May, 1998Gorowitz et al. 257/522
5,801,444Sept., 1998Aboelfotah et al. 257/742

Foreign Patent Documents
5-275682Oct., 1993JP 257/742
Other References

Berezhnoi, A., Silicon and its Binary Systems, Consultants Bureau, New York, 84, (1960).

Fukuda, Y., et al., "A New Fusible-Type Programmable Element Composed of Aluminum and Polysilicon", IEEE Trans. on Electron Devices, ED-33, 250-253, (Feb., 1986).

Hanna, J., et al., "Early Stage of Polycrystalline Growth of Ge and SiGe by Reactive Thermal CVD from GeF(4) and Si(2)H(6)", Materials Res. Soc. Symp. Proc., 358, Boston, MA, 877-881, (Nov./Dec., 1994).

Hansen, P., Constitution of Binary Alloys, McGraw-Hill, New York, 103, (1958).

Hiraki, A., et al., "Formation of Silicon Oxide over Gold Layers on Silicon Substrates", J. Applied Physics, 43, 3643-3649, (Sep., 1972).

Hiraki, A., et al., "Low-Temperature Migration of Silicon in Metal Films on Silicon Substrates Studiedby Backscattering Techniques", J. Vacuum Science and Tech., 9, 155-158, (Jan./Feb., 1972).

Horie, H., et al., "Novel High Aspect Ratio Aluminum Plug for Logic/DRAM LSI's Using Polysilicon-Aluminum Substitute", Technical Digest: IEEE Int. Electron Devices Meeting, San Francisco, CA, 946-948, (1996).

Hurley, P., et al., "Low Temperature Plasma Oxidation of Polycrystalline Silicon", Proc. 7th European Conf. on Insulating Films on Semiconductors: Contributed Papers, Section 5, IOP Publishing Ltd., 235-238, (1991).

King, T., et al., "Deposition and Properties of Low-Pressure Chemical-Vapor Deposited Polycrystalline Silicon-Germanium Films", J. Electrochemical Society, 141, 2235-2241, (Aug. 1994).

Lee, D.H., et al., "Gate Oxide Integrity (GOI) of MOS transistors with W/TiN stacked gate", 1996 Symposium on VLSI Technology Digest of Technical Papers, 208-209, (1996).

Li, C., et al., "Low Temperature Heteroepitaxial Growth of Si(1-x)Ge(x)-on-Si by Photo-Enhanced Ultra High Vacuum Chemical Vapor Chemical Vapor Deposition Using Si(2)H(6) and Ge(2)H(6)", J. Electronic Materials, 24, 875-884, (Jul. 1995).

Li, P., et al., "Formation of Stoichiometric SiGe Oxide by Electron Cyclotron Resonance Plasma", Appl. Phys. Lett, 60, 3265-3267, (Jun. 1992).

Lyman, T.e., "Metallography, Structure and Phase Diagrams", Metals Handbook, 8, American Society for Metals; Metals Park, Ohio, 253, 256, 260, 263,, (1989).

Moffatt, W., The Handbook of Binary Phase Diagrams, General Electric Company, pub., vol. 1, 3/84, (1978).

Mohajerzadeh, S., et al., "A Low Energy Ion Beam Assisted Deposition Technique for Realizaing iso-type SiGe/Si hetero-interface diodes", Thin Solid Films, 283, 182-187, (1996).

Mohajerzadeh, S., et al., "A Low-Temperature Ion Vapor Deposition Technique for Silicon and Silicon-Germanium Epitaxy", Canadian J. Physics, 74, S69-S73, (1996).

Mohri, M., et al., "Effect of SiF(4)/SiH(4)/H(2) Flow Rates on Film Properties of Low-Temperature Polycrystalline Silicon Films Prepared by Plasma Enchanced Chemical Vapor Deposition", IEICE Transactions on Electronics, E77-C, 1677-1684, (Oct. 1994).

Mukhopadhyay, M., et al., "Properties of SiGe Oxides Grown in a Microwave Oxygen Plasma", J. Applied Physics, 78, 6135-6140, (Nov. 1995).

Predel, B., et al., "Die Zustandsdiagramme Silber-Germanium-Silizium und Gold-Germanium-Silizium", J. Less-Common Metals, 44, 39-49, (Jan. 1976).

Schadel, H., et al., "Activity of Liquid Silver-Silicon Alloys", Trans. American Institute of Mining and Metallurgical Engineers, 188, 1282-1283, (Oct. 1950).

Ushiku, Y., et al., "Planarized Silver Interconnect Technology with a Ti Self-Passivation Technique for Deep Sub-Micron ULSIs", 1993 Symp. on VLSI Technology: Digest of Technical Papers, 121-122, (1993).

Wu, S., et al., "Suppression of the Boron Penetration Induced Si/SiO2 Interface Degradation by Using a Stacked-Amorphous-Silicon Film as the Gate Structure for pMOSFET", IEEE Electron Device Letters, 15, 160-162, (May 1994).

Primary Examiner: Martin-Wallace; Valencia
Assistant Examiner: Clark; S. V.
Attorney, Agent or Firm: Schwegman, Lundberg, Woessner & Kluth, P.A.
17 Claims, 12 Drawing Figures

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