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| United States Patent | 5,981,350 |
| Geusic, et. al. | Nov. 9, 1999 |
Abstract
A method and structure for high capacitance memory cells is provided. The method includes forming a trench capacitor in a semiconductor substrate. A self-structured mask is formed on the interior surface of the trench. The interior surface of the trench is etched to form an array of silicon pillars. The self-structured mask is removed. Then an insulator layer is formed on the array of silicon pillars. A polycrystalline semiconductor plate extends outwardly from the insulator layer in the trench.
| Inventors: | Geusic; Joseph E. (Berkeley Heights, NJ); Forbes; Leonard (Corvallis, OR); Ahn; Kie Y. (Chappaqua, NY). |
| Assignee: | Micron Technology, Inc. (Boise, ID). |
| Appl. No.: | 87,480 |
| Filed: | May 29, 1998 |
| Intl. Cl. : | H01L 21/20 |
| Current U.S. Cl.: | 438/386; 438/243; 438/398 |
| Field of Search: | 438/386, 387, 391, 396, 398, 243, 244, 248, 253, 255 |
| 4,906,590 | Mar., 1990 | Kanetaki et al. | 438/386 |
| 4,977,436 | Dec., 1990 | Tsuhiya et al. | 357/236 |
| 5,001,526 | Mar., 1991 | Gotou | 357/23.6 |
| 5,006,909 | Apr., 1991 | Kosa | 357/23.6 |
| 5,153,813 | Oct., 1992 | Oehrlein et al. | 438/386 |
| 5,166,762 | Nov., 1992 | Yoshida | 257/302 |
| 5,176,789 | Jan., 1993 | Yamazaki et al. | 438/700 |
| 5,191,509 | Mar., 1993 | Wen | 361/311 |
| 5,204,280 | Apr., 1993 | Dhong et al. | 438/386 |
| 5,360,758 | Nov., 1994 | Bronner et al. | 438/386 |
| 5,393,683 | Feb., 1995 | Mathews et al. | 437/42 |
| 5,401,681 | Mar., 1995 | Dennison | 437/60 |
| 5,407,534 | Apr., 1995 | Thakur | 156/662 |
| 5,438,011 | Aug., 1995 | Blalock et al. | 437/52 |
| 5,592,412 | Jan., 1997 | Kleinhenz et al. | 438/386 |
| 5,658,816 | Aug., 1997 | Rajeevakumar | 438/386 |
| 5,662,768 | Sept., 1997 | Rostoker | 438/386 |
| 5,719,080 | Feb., 1998 | Kenney | 438/386 |
| 5,766,698 | Jun., 1998 | Armacost et al. | 438/700 |
Abstract of Japanese Patent Application No. JP 363066963, published Mar. 25, 1988, from JPO & JAPIO, (1998).
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