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United States Patent 5,981,350
Geusic, et. al. Nov. 9, 1999

Method for forming high capacitance memory cells


A method and structure for high capacitance memory cells is provided. The method includes forming a trench capacitor in a semiconductor substrate. A self-structured mask is formed on the interior surface of the trench. The interior surface of the trench is etched to form an array of silicon pillars. The self-structured mask is removed. Then an insulator layer is formed on the array of silicon pillars. A polycrystalline semiconductor plate extends outwardly from the insulator layer in the trench.

Inventors: Geusic; Joseph E. (Berkeley Heights, NJ); Forbes; Leonard (Corvallis, OR); Ahn; Kie Y. (Chappaqua, NY).
Assignee: Micron Technology, Inc. (Boise, ID).
Appl. No.: 87,480
Filed: May 29, 1998
Intl. Cl. : H01L 21/20
Current U.S. Cl.: 438/386; 438/243; 438/398
Field of Search: 438/386, 387, 391, 396, 398, 243, 244, 248, 253, 255

References Cited | [Referenced By]

U.S. Patent Documents
4,906,590Mar., 1990Kanetaki et al. 438/386
4,977,436Dec., 1990Tsuhiya et al. 357/236
5,001,526Mar., 1991Gotou 357/23.6
5,006,909Apr., 1991Kosa 357/23.6
5,153,813Oct., 1992Oehrlein et al. 438/386
5,166,762Nov., 1992Yoshida 257/302
5,176,789Jan., 1993Yamazaki et al. 438/700
5,191,509Mar., 1993Wen 361/311
5,204,280Apr., 1993Dhong et al. 438/386
5,360,758Nov., 1994Bronner et al. 438/386
5,393,683Feb., 1995Mathews et al. 437/42
5,401,681Mar., 1995Dennison 437/60
5,407,534Apr., 1995Thakur 156/662
5,438,011Aug., 1995Blalock et al. 437/52
5,592,412Jan., 1997Kleinhenz et al. 438/386
5,658,816Aug., 1997Rajeevakumar 438/386
5,662,768Sept., 1997Rostoker 438/386
5,719,080Feb., 1998Kenney 438/386
5,766,698Jun., 1998Armacost et al. 438/700

Other References

Abstract of Japanese Patent Application No. JP 363066963, published Mar. 25, 1988, from JPO & JAPIO, (1998).

Primary Examiner: Nguyen; Tuan H.
Attorney, Agent or Firm: Schwegman, Lundberg, Woessner & Kluth P.A.
20 Claims, 9 Drawing Figures

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