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United States Patent 6,072,209
Noble, et. al. Jun. 6, 2000

Four F.sup.2 folded bit line DRAM cell structure having buried bit and word lines

Abstract

A memory cell structure for a folded bit line memory array of a dynamic random access memory device includes buried bit and word lines, with the access transistors being formed as a vertical structure on the bit lines. Isolation trenches extend orthogonally to the bit lines between the access transistors of adjacent memory cells, and a pair of word lines are located in each of the isolation trenches. The word lines are oriented vertically widthwise in the trench and are adapted to gate alternate access transistors, so that both an active and a passing word line can be contained within each memory cell to provide a folded bit line architecture. The memory cell has a surface area that is approximately 4 F(^2), where F is a minimum feature size. Also disclosed are processes for fabricating the DRAM cell using bulk silicon or a silicon on insulator processing techniques.


Inventors: Noble; Wendell P. (Milton, VT); Forbes; Leonard (Corvallis, OR); Ahn; Kie Y. (Chappaqua, NY).
Assignee: Micro Technology, Inc. (Boise, ID).
Appl. No.: 889,463
Filed: Jul. 8, 1997
Intl. Cl. : H01L 27/108
Current U.S. Cl.: 257/296; 257/306; 257/334
Field of Search: 257/302, 306, 296, 330, 334, 907

References Cited | [Referenced By]

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5,646,900Jul., 1997Tsukude et al. 365/205
5,691,230Nov., 1997Forbes 437/62
5,753,947May, 1998Gonzalez 257/308

Foreign Patent Documents
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Primary Examiner: Prenty; Mark V.
Attorney, Agent or Firm: Schwegman, Lundberg, Woessner & Kluth,P.A.
17 Claims, 22 Drawing Figures

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