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United States Patent 6,093,623
Forbes Jul. 25, 2000

Methods for making silicon-on-insulator structures

Abstract

Some advanced integrated circuits are fabricated as silicon-on-insulator structures, which facilitate faster operating speeds, closer component spacing, lower power consumption, and so forth. Unfortunately, current bonded-wafer techniques for making such structures are costly because they waste silicon. Accordingly, one embodiment of the invention provides a smart-bond technique that allows repeated use of a silicon wafer to produce hundreds and potentially thousands of silicon-on-insulator structures, not just one or two as do conventional methods. More precisely, the smart bond technique entails bonding selected first and second regions of a silicon substrate to an insulative substrate and then separating the two substrates to leave silicon protrusions or islands on the insulative substrate. The technique is also suitable to forming three-dimensional integrated circuits, that is, circuits having two or more circuit layers.


Inventors: Forbes; Leonard (Corvallis, OR).
Assignee: Micron Technology, Inc. (Boise, ID).
Appl. No.: 128,851
Filed: Aug. 4, 1998
Intl. Cl. : H01L 21/30
Current U.S. Cl.: 438/455; 438/459
Field of Search: 438/455, 459, 977, 406, 151

References Cited | [Referenced By]

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Primary Examiner: Niebling; John F.
Assistant Examiner: Lindsay, Jr.; Walter L.
Attorney, Agent or Firm: Schwegman, Lundberg, Woessner & Kluth, P.A.Drake; Eduardo E.
16 Claims, 9 Drawing Figures

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