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United States Patent 6,097,242
Forbes, et. al. Aug. 1, 2000

Threshold voltage compensation circuits for low voltage and low power CMOS integrated circuits


A compensation circuit for transistor threshold voltages in integrated circuits is described. The compensation circuit includes a transistor, current source, and gate reference voltage supply. The transistor is biased to provide a well bias voltage, or backgate voltage V(BG), which is coupled to transistors provided on a common integrated circuit. This compensation circuit eliminates the need for gate biasing capacitors, and provides flexibility in setting threshold voltages in low voltage circuits. The gate reference voltage and current source are established to provide a desired backgate voltage V(BG). Compensation circuits are described for both n-channel and p-channel transistors. A memory device is described which includes compensation circuits for controlling threshold voltages of transistors provided therein.

Inventors: Forbes; Leonard (Corvallis, OR); Ahn; Kie Y. (Chappaqua, NY).
Assignee: Micron Technology, Inc. (Boise, ID).
Appl. No.: 31,976
Filed: Feb. 26, 1998
Intl. Cl. : G05F 3/02
Current U.S. Cl.: 327/537; 327/534
Field of Search: 327/534, 537, 543; 365/226

References Cited | [Referenced By]

U.S. Patent Documents
3,657,575Apr., 1972Taniguchi et al. 327/541
3,806,741Apr., 1974Smith 327/537
5,292,676Mar., 1994Manning 438/197
5,385,854Jan., 1995Batra et al. 438/163
5,451,889Sept., 1995Heim et al. 326/81
5,502,629Mar., 1996Ito et al. 363/60
5,789,967Aug., 1998Katoh 327/408
5,821,796Oct., 1998Yaklin et al. 327/313
5,852,375Dec., 1998Byrne et al. 327/108
5,909,400Jun., 1999Bertin et al. 365/177
5,926,412Jul., 1999Evans, Jr. et al. 365/145
5,963,469Oct., 1999Forbes 365/149

Other References

Asai, S., et al., "Technology Challenges for Integration Near and Below 0.1 micrometer", Proceedings of the IEEE, 85, Special Issue on Nanometer-Scale Science & Technology, 505-520, (Apr. 1997).

Askin, H.O., et al., "Fet Device Parameters Compensation Circuit", IBM Technical Disclosure Bulletin, 14, 2088-2089, (Dec. 1971).

Blalock, T.N., et al., "A High-Speed Sensing Scheme for 1T Dynamic RAM's Utilizing the Clamped Bit-Line Sense Amplifier", IEEE Journal of Solid-State Circuits, 27, 618-625, (Apr. 1992).

Burnett, D., et al., "Implications of Fundamental Threshold Voltage Variations for High-Density SRAM and Logic Circuits", 1994 Symposium on VLSI Technology, Digest of Technical Papers, Honolulu, HI, 15-16, (Jun. 4-7, 1994).

Burnett, D., et al., "Statistical Threshold-Voltage Variation and its Impact on Supply-Voltage Scaling", Proceedings SPIE: Microelectronic Device and Multilevel Interconnection Technology, 2636, 83-90, (1995).

Chen, M., et al., "Back-Gate Forward Bias Method for Low Voltage CMOS Digital Circuits", IEEE Transactions on Electron Devices, 43, 904-909, (1996).

Clemen, R., et al., "VT-compensated TTL-Compatible Mos Amplifier", IBM Technical Disclosure Bulletin, 21, 2874-2875, (1978).

De, V.K., et al., "Random Mosfet Parameter Fluctuation Limits to Gigascale Integration (GST)", Symposium on VLSI Technology Digest of Technical Papers, 198-199, (1996).

DeBar, D.E., "Dynamic Substrate Bias to Achieve Radiation Hardening", IBM Technical Disclosure Bulletin, 25, 5829-5830, (1983).

Forbes, L., "Automatic On-clip Threshold Voltage Compensation", IBM Technical Disclosure Bulletin, 14, 2894-2895, (1972).

Frantz, H., et al., "Mosfet Substrate Bias-Voltage Generator", IBM Technical Disclosure Bulletin, 11, 1219-1220, (Mar. 1969).

Fuse, T., et al., "A 0.5V 200MHz 1-Stage 32b ALU Using a Body Bias Controlled SOI Pass-Gate Logic", 1997 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 286-287, (1997).

Puri, Y., "Substrate Voltage Bounce in NMOS Self-biased Substrates", IEEE Journal of Solid-State Circuits, SC-13, 515-519, (Aug. 1978).

Saito, M., et al., "Technique for Controlling Effective Vth in Multi-Gbit DRAM Sense Amplifier", 1996 Symposium on VLSI Circuits, Digest of Technical Papers , Honolulu, HI, 106-107, (Jun. 13-15, 1996).

Sherony, M.J., et al., "Reduction of Threshold Voltage Sensitivity in SOI MOSFET's", IEEE Electron Device Letters, 16, 100-102, (Mar. 1995).

Shimomura, K., et al., "A 1V 46ns 16Mb SOI-DRAM with Body Control Technique", 1997 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 68-69, (Feb. 6, 1997).

Yoshikawa, K., "Impact of Cell Threshold Voltage Distribution in the Array of Flash Memories on Scaled and Multilevel Flash Cell Design", 1996 Symposium on VSLI Technology, Digest of Technical Papers, Honolulu, HI, 240-241, (Jun. 11-13, 1996).

Primary Examiner: Cunningham; Terry D.
Attorney, Agent or Firm: Schwegman, Lundberg, Woessner & Kluth, P.A.
29 Claims, 11 Drawing Figures

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