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United States Patent 6,104,045
Forbes, et. al. Aug. 15, 2000

High density planar SRAM cell using bipolar latch-up and gated diode breakdown

Abstract

Area efficient static memory cells and arrays containing p-n-p-n or n-p-n-p transistors which can be latched-up in a bistable on state. Each transistor memory cell includes a gate which is pulse biased during the write operation to latch-up the cell. Also provided are linked memory cells in which the transistors share common regions.


Inventors: Forbes; Leonard (Corvallis, OR); Noble, Jr.; Wendell P. (Milton, VT).
Assignee: Micron Technology, Inc. (Boise, ID).
Appl. No.: 76,745
Filed: May 13, 1998
Intl. Cl. : H01L 29/74, H01L 27/11
Current U.S. Cl.: 257/141; 257/140; 257/162; 257/175; 257/180; 257/903; 365/175; 365/180
Field of Search: 257/903, 140, 141, 162; 365/175, 180

References Cited | [Referenced By]

U.S. Patent Documents
4,543,595Sept., 1985Vora 365/175
4,720,845Jan., 1988Lechner 379/27
5,173,754Dec., 1992Manning
5,214,295May, 1993Manning
5,286,663Feb., 1994Manning
5,486,717Jan., 1996Kokubo et al.
5,497,011Mar., 1996Terashima
5,535,156Jul., 1996Levy et al.
5,581,104Dec., 1996Lowry et al.
5,594,683Jan., 1997Chen et al.
5,624,863Apr., 1997Helm et al.
5,650,350Jul., 1997Dennison et al.
5,684,737Nov., 1997Wang 365/175
5,705,843Jan., 1998Roberts
5,710,741Jan., 1998McLaury

Other References

D. L. Hetherington et al, An Integrated GaAs N-P-N-P Thyristor/JFET Memory Cell Exhibiting Nondestructive Read, IEEE Electron Device Letters, vol. 13, No. 9, Sep. 1992.

S. V. Vandebroek et al, High-Gain Lateral Bipolar Action in a MOSFET Structure, IEEE Transactions on Electron Devices, vol. 38, No. 11, Nov. 1991.

J.J. Ebers, Four-Terminal P-N-P-N Transistors, Proceedings of IRE, Nov. 1952, pp. 1361-1364.

I.T. Ho et al, Single Thyuristor Static Memory and its Fabrication, vol. 23, No.3, 1980.

S. M. Sze, Physics of Semiconductor Devices, Second Edition, A Wiley Interscience Pub. 1981.

S.D. Malaviya, Single-Device DC Stable Memory Cell, IBM Technical Disclosure Bulletin, vol. 20, No. 9, pp. 3492-3494, Nov. 1978.

R. C. Fang, Latchup Model for the Parasitic P-N-P-N Path in Bulk CMOS, IEEE Transactions on Electron Devices, vol. Ed. 31, No. Jan. 1984.

R. R. Troutman et al. Transient Analysis of Latchup in Bulk CMOS, IEEE Transactions on Electron Devices, vol. Ed. 30, No. 2, Feb. 1993.

Farid Nemati et al, "A Novel High Density, Low Voltage SRAM Cell With a Vertical NDR Device", Center for Integrated Systems, Stanford University, CA, (2 pages).

Hyun-Jin Cho et al, "A Novel Pillar DRAM Cell for 4GBIT and Beyond", Center for Integrated Systems, Stanford University, CA, (2 pages).

(For both A and B citations above--published in IEEE 1998, Symposium on VLSI Technology, Honolulu, Hawaii, Jun. 9th and 11th, 1998).


Primary Examiner: Jackson, Jr.; Jerome
Attorney, Agent or Firm: Dickstein Shapiro Morin & Oshinsky LLP
47 Claims, 17 Drawing Figures

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