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|United States Patent||6,104,068|
|Forbes||Aug. 15, 2000|
An improved structure and method are provided for signal processing. The structure includes dual-gated metal-oxide semiconducting field effect transistor (MOSFET). The dual-gated MOSFET can be fabricated according to current CMOS processing techniques. The body region of the dual-gated MOSFET is a fully depleted structure. The structure includes two gates which are positioned on opposite sides of the opposing sides of the body region. Further, the structure operates as one device where the threshold voltage of one gate depends on the bias of the other gate. Thus, the structure yields a small signal component in analog circuit applications which depends on the product of the signals applied to the gates, and not simply one which depends on the sum of the two signals.
|Inventors:||Forbes; Leonard (Corvallis, OR).|
|Assignee:||Micron Technology, Inc. (Boise, ID).|
|Filed:||Sept. 1, 1998|
|Intl. Cl. :||H01L 29/78, H01L 29/80|
|Current U.S. Cl.:||257/365; 257/401; 257/623|
|Field of Search:||257/365, 401, 423; 327/105|
Mitano et al, High Speed... Trench MOSFET with Dual Gate, VLSI Symposium Digest, 1988.
GaAs IC Symposium, IEEE Gallium Arsenide Integrated Cisuit Symposium, 19th Annual Technical Digest, Anaheim, California, pp. 1-290, (Oct. 12-15, 1997).
Asai, S., et al., "The GaAs Dual-Gate Fet With Low Noise And Wide Dynamic Range", Technical Digest, International Electron Devices Meeting, pp. 64-67, (Dec. 1973).
Colinge, J.P., "Reduction of Kink Effect in Thin-Film SOI MOSFET's", IEEE Electron Device Letters, 9(2), pp. 97-99, (1988).
Denton, J.P., et al., "Fully Depleted Dual-Gated Thin-Film SOI P-MOSFET's Fabricated in SOI Islands with an Isolated Buried Polysilicon Backgate", IEEE Electron Device Letters, 17(11), 509-511, (Nov. 1996).
Nishinohara, K., et al., "Effects of Microscopic Fluctuations in Dopant Distributions on MOSFET Threshold Voltage", IEEE Transactions on Electron Devices, 39(3), pp. 634-639, (Mar. 1992).
Stolk, P.A., et al., "The Effect of Statistical Dopant Fluctuations on MOS Device Performance", IEEE, pp. 23.4.1-23.4.4, (1996).
Takeuchi, K., et al., "Channel Engineering for the Reduction of Random-Dopant-Placement-Induced Threshold Voltage Fluctuations", IEEE, pp. 33.6.1-33.6.4, (1997).
Taur, Y., et al., "CMOS Devices below 0.1 micrometer: How High Will Performance Go?", IEEE, pp. 9.1.1-9.1.4, (1997).
Wong, H.S., et al., "Self-Aligned (Top and Bottom) Double-Gate MOSFET with a 25 nm Thick Silicon Channel", IEEE, pp. 16.6.1-16.6.4, (1997).
Wong, H.S., et al., "Three-Dimensional "Atomistic" Simulation of Discrete Random Dopant Distribution Effects in Sub-0.1 micrometer MOSFET's", IEEE, pp., 29.2.1-29.2.4, (1993).
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