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|United States Patent||6,125,062|
|Ahn, et. al.||Sept. 26, 2000|
A memory device and related methods are described. The memory device includes a plurality of cells, each cell including a MOSFET having a source coupled to a first end of a channel, a drain coupled to a second end of the channel, a gate formed on a gate insulator and extending from the source to the drain and a plurality of conductive islands, each surrounded by an insulator, formed in the channel. The islands have a maximum dimension of three nanometers. The surrounding insulator has a thickness of between five and twenty nanometers. Each island and surrounding insulator is formed in a pore extending into the channel. As a result, the memory cells are able to provide consistent, externally observable changes in response to the presence or absence of a single electron on the island.
|Inventors:||Ahn; Kie (Chappaqua, NY); Forbes; Leonard (Corvallis, OR).|
|Assignee:||Micron Technology, Inc. (Boise, ID).|
|Filed:||Aug. 26, 1998|
|Intl. Cl. :||G11C 7/00|
|Current U.S. Cl.:||365/189.07; 257/314|
|Field of Search:||257/314, 315, 321; 365/189.07|
|5,731,598||Mar., 1998||Kado et al.||257/30|
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