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United States Patent 6,128,216
Noble, Jr., et. al. Oct. 3, 2000

High density planar SRAM cell with merged transistors

Abstract

Area efficient static memory cells and arrays containing p-n-p-n or n-p-n-p transistors which can be latched-up in a bistable on state. Each transistor memory cell includes gates which are pulse biased during the write operation to latch-up the cell. Also provided are linked memory cells in which the transistors share common regions.


Inventors: Noble, Jr.; Wendell P. (Milton, VT); Forbes; Leonard (Corvallis, OR).
Assignee: Micron Technology Inc. (Boise, ID).
Appl. No.: 76,766
Filed: May 13, 1998
Intl. Cl. : G11C 11/00, G11C 11/36
Current U.S. Cl.: 365/154; 365/156; 365/175
Field of Search: 365/175, 180, 181, 154, 156

References Cited | [Referenced By]

U.S. Patent Documents
3,729,719Apr., 1973Wiedmann 365/180
4,654,824Mar., 1987Thomas et al. 365/175
4,912,675Mar., 1990Blake et al. 365/154
5,173,754Dec., 1992Manning 357/23.7
5,214,295May, 1993Manning 257/67
5,276,638Jan., 1994Wong 365/156
5,286,663Feb., 1994Manning 437/41
5,486,717Jan., 1996Kokubo et al. 257/385
5,497,011Mar., 1996Terashima 257/147
5,535,156Jul., 1996Levy et al. 365/175
5,581,104Dec., 1996Lowrey et al. 257/355
5,594,683Jan., 1997Chen et al. 365/177
5,624,863Apr., 1997Helm et al. 438/210
5,650,350Jul., 1997Dennison et al. 437/52
5,705,843Jan., 1998Roberts 257/379
5,710,741Jan., 1998McLaury 365/226

Other References

R. C. Fang, Latchup Model for the Parasitic P-N-P-N Path in Bulk CMOS, IEEE Transactions on Electron Devices, vol. Ed. 31, No. 1, Jan. 1984.

R. R. Troutman et al, Transient Analysis of Latchup in Bulk CMOS, IEEE Transactions on Electron Devices, vol. Ed. 30, No. 2, Feb. 1993.

D. L. Hetherington et al, An Intergrated GaAs N-P-N-P Thyristor/JFET Memory Cell Exhibiting Nondestructive Read, IEEE Electron Device Letters, vol. 13, No. 9, Sep. 1992.

S. V. Vandebroek et al, High-Gain Lateral Bipolar Action in a MOSFET Structure, IEEE Transactions on Electron Devices, vol. 38, No. 11, Nov. 1991.

Dermot MacSweeney et al., Modeling of Lateral Bipolar Devices in a CMOS, IEEE BCTM 1.4, 4 pages.

J.J. Ebers, Four-Terminal P-N-P-N Transistors, Proceedings of IRE, Nov. 1952, p. 1361-4.

I.T. Ho et al, Single Thyristor Static Memory and its fabrication, vol. 23, No. 3, 1980.

B.L. Gregory et al, Latchup in CMOS integrated circuits, Sandia Laboratories, p. 12-18.

S. M. Sze, Physics of Semiconductor Devices, Second Edition, A Wiley Interscience Pub.

S.D. Malaviya, Single-Device DC Stable Memory Cell, IBM Technical Disclosure Bulletin, vol. 20, No. 9, pp 3492-94, Nov. 1978.

Farid Nemati et al, "A Novel High Density, Low Voltge SRAM Cell with a Vertical NDR Device", Center for Integrated Systems, Stanford University, Stanford, CA, (2 pages), published in IEEE 1998, Symposium on VLSI Technology, Honolulu, Hawaii, Jun. 9th and 11th, 1998.

Hyun-Jin Cho et al, "A Novel Pillar DRAM Cell for 4GBIT and Beyond", Center for Integrated Systems, Stanford University, Stanford, CA, (2 pages), published in IEEE 1998, Symposium on VLSI Technology, Honolulu, Hawaii, Jun. 9th and 11th, 1998.


Primary Examiner: Mai; Son
Attorney, Agent or Firm: Dickstein Shapiro Morin & Oshinsky LLP
51 Claims, 17 Drawing Figures

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