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United States Patent 6,141,238
Forbes, et. al. Oct. 31, 2000

Dynamic random access memory (DRAM) cells with repressed ferroelectric memory methods of reading same, and apparatuses including same

Abstract

A memory cell having first and second operating modes includes a transistor comprising a gate adjacent to a channel region coupling source and drain regions, a digitline coupled to one of the source and drain regions, a storage capacitor coupled to the other of the source and drain regions, a ferroelectric capacitor, and a wordline coupled to the gate by the ferroelectric capacitor. Preferably, data is written to and read out of the storage capacitor during the first operating mode and written to and read out of the ferroelectric capacitor during the second mode of operation. A memory cell array, a memory module, and a processor based system can all be fabricated from this memory cell. A method for reading data out of the memory cell in first and second operating modes is also described.


Inventors: Forbes; Leonard (Corvallis, OR); Ahn; Kie Y. (Chappaqua, NY); Noble; Wendell P. (Milton, VT); Reinberg; Alan R. (Westport, CT).
Assignee: Micron Technology, Inc. (Boise, ID).
Appl. No.: 385,380
Filed: Aug. 30, 1999
Intl. Cl. : G11C 11/22
Current U.S. Cl.: 365/145; 365/149
Field of Search: 365/145, 149

References Cited | [Referenced By]

U.S. Patent Documents
4,888,733Dec., 1989Mobley 365/145
5,345,415Sept., 1994Nakao et al. 365/145
5,399,516Mar., 1995Bergendahl et al. 438/589
5,497,494Mar., 1996Combs et al. 395/750.05
5,530,668Jun., 1996Chern et al. 365/145
5,539,279Jul., 1996Takeuchi et al. 365/145
5,541,871Jul., 1996Nishimura et al. 365/145
5,541,872Jul., 1996Lowery et al. 365/145
5,550,770Aug., 1996Kuroda 365/145
5,572,459Nov., 1996Wilson et al. 365/145
5,600,587Feb., 1997Koike 365/145
5,603,011Feb., 1997Piazza 711/170
5,619,642Apr., 1997Nielson et al. 395/182.04
5,640,030Jun., 1997Kenney 257/296
5,689,456Nov., 1997Kobayashi 365/145
5,768,185Jun., 1998Nakamura et al. 365/145
5,856,688Jan., 1999Lee et al. 257/295
5,903,492May, 1999Takashima 365/145

Other References

Takashima et al.; "A sub-40ns Random-Access Chain FRAM Architecture with a 7ns Cell-Plate-Line Drive"; IEEE International Solid-State Circuits Conference, 1999, pp. 102, 103 and 450.

Miyakawa et al.; "A 0.5 mum 3V 1T1C 1 Mb FRAM with a Variable Reference Bitline Voltage Scheme using a Fatigue-Free Reference Capacitor"; IEEE International Solid-State Circuit Conference, 1999, pp. 104, 105 and 450.

Asari et al; "Multi-Mode and Multi-Level Technologies for FeRAM Embedded Reconfigurable Hardware"; IEEE International Solid-State Circuits Conference, 1999, pp. 106, 107 and 451.

Kang et al.; "Multi-Phase-Driven Split-Word-Line Ferroelectric Memory without Plate Line", IEEE International Solid-State Circuits Conference, 1999, pp. 108-109.

Cuppens et al.; "Ferroelectrics for non-volatile memories", Microelectronic Engineering 19, (1992), pp. 245-252.

Arita et al.; "Characterization of Ferroelectric Gate MOS Capacitors Formed by MOD Technique for Nonvolatile Memory Applications"; Integrated Ferroelectrics, 1998 vol. 2, pp. 143-152.

Torii et al.; "Properties of ultra-thin lead zirconate titanate thin films prepared by ozone jet reactive evaporation"; J. Appl. Phys. vol. 81, No. 6, Mar. 1997, pp. 2755-2759.

Tuttle et al; "Ferroelectric Thin Films IV"; Material Research Society Symposium Proceedings, vol. 361, 1994, pp. 249-254.

Amanuma et al.; "Preparation and Ferroelectric properties of SrBi(2) Ta(2) O(9) thin films"; Appl Phys. Lett vol. 66, No. 2, Jan. 1995, pp. 221-223.

Onishi et al.; "A Half-Micron Ferroelectric Memory Cell Technology with Stacked Capacitor Structure"; IEEE 1994, pp. 843-846.

Sheikholeslami; "Transient modeling of Ferroelectric Capacitors for Semiconductor Memories"; Thesis, University of Toronto; 1994; pp. 1-66.

Tanabe et al.; "A High Density 1T/2C Cell with Vcc/2 Reference Level for high Stable FeRAMs"; IEEE 1997, pp. 863-866.

Kokie et al.; "A 60-ns 1-Mb Nonvolatile Ferroelectric Memory with a Nondriven Cell Plate Line Write/Read Scheme"; IEEE Journal of Solid-State Circuits; vol. 31, No. 11, Nov. 1996, pp. 1625-1634.

Tuttle et al; "Ferroelectric Thin Films IV"; Material Research Society Symposium Proceedings, vol. 361, 1994, pp. 409-414.

Koike et al.; "A 60-ns 1-Mb Nonvolatile Ferroelectric Memory with a Non-driven Cell Plate Line Write/Read Scheme"; IEEE International Solid-State Circuits Conference, 1996, pp. 368-369.

Ramer et al.; "Ferrolelectric Capacitor Nondestructive Readout Memory"; Integrated Ferroelectircs 1995 vol. 11, pp. 171-177.

Fujisawa et al.; "The Charge-Share Modified (CSM) Precharge-Level Architecture for High-Speed and Low-Power Ferroelectric Memory"; IEEE Journal of Solid-State Circuits, vol. 32, No. 5, May 1997, pp. 655-661.


Primary Examiner: Phan; Trong
Attorney, Agent or Firm: Dickstein Shapiro Morin & Oshinsky LLP
61 Claims, 33 Drawing Figures

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