[Help]Full Text[Boolean Search][Advanced][Number Search][Order Copy][PTDLs]

[Previous Patent] [Next Patent] [Back to List]
(2 of 59)


United States Patent 6,150,188
Geusic, et. al. Nov. 21, 2000

Integrated circuits using optical fiber interconnects formed through a semiconductor wafer and methods for forming same

Abstract

An integrated circuit with a number of optical fibers that are formed in high aspect ratio holes. The high aspect ratio holes extend through a semiconductor wafer. The optical fibers include a cladding layer and a core formed in the high aspect ratio hole. These optical fibers are used to transmit signals between functional circuits on the semiconductor wafer and functional circuits on the back of the wafer or beneath the wafer.


Inventors: Geusic; Joseph E. (Berkeley Heights, NJ); Ahn; Kie Y. (Chappaqua, NY); Forbes; Leonard (Corvallis, OR).
Assignee: Micron Technology Inc. (Boise, ID).
Appl. No.: 31,975
Filed: Feb. 26, 1998
Intl. Cl. : H01L 21/00
Current U.S. Cl.: 438/31; 438/107; 438/456; 438/65
Field of Search: 438/29, 31, 455, 667, 27, 46, 65, 67, 69, 93, 107, 108, 956; 257/686, 432

References Cited | [Referenced By]

U.S. Patent Documents
3,968,564Jul., 1976Springthorpe 29/580
4,744,623May, 1988Prucnal et al. 350/96.2
4,920,070Apr., 1990Mukai 437/173
4,970,578Nov., 1990Tong et al. 357/81
5,128,831Jul., 1992Fox, III et al.
5,221,633Jun., 1993Holm et al. 437/51
5,352,998Oct., 1994Tamino 333/247
5,362,976Nov., 1994Suzuki 257/81
5,409,563Apr., 1995Cathey 156/643
5,489,554Feb., 1996Gates 437/208
5,532,506Jul., 1996Tserng et al. 257/276
5,604,835Feb., 1997Nakamura et al. 385/129
5,641,545Jun., 1997Sandhu 427/573
5,656,548Aug., 1997Zavracky et al. 438/23
5,682,062Oct., 1997Gaul 257/686
5,729,038Mar., 1998Young et al. 257/460
5,742,100Apr., 1998Schroeder et al. 257/778
5,760,478Jun., 1998Bozso et al. 257/777
5,767,001Jun., 1998Bertagnolli et al. 438/455
5,798,297Aug., 1998Winnerl et al. 438/622
5,834,849Nov., 1998Lane 257/786
5,844,289Dec., 1998Teranishi et al. 257/432
5,858,814Jan., 1999Goossen et al. 438/107
5,897,333Apr., 1999Goossen et al. 438/455
5,900,674May, 1999Wojnarowski et al. 257/774
5,901,050May, 1999Imai 361/820
5,902,118May, 1999Hubner 438/106
5,903,045May, 1999Bertin et al. 257/621
5,915,167Jun., 1999Leedy 438/108
5,952,665Sept., 1999Bhargava 250/483.1

Foreign Patent Documents
3-13907Mar., 1991JP
404263462ASept., 1992JP
405145060AJun., 1993JP
91/11833Aug., 1991WO
94/05039Mar., 1994WO
Other References

Forbes, L., et al., "Resonant Forward-Biased Guarding-Ring Diodes for Suppression of Substrate Noise in Mixed-Mode CMOS Circuits", Electronics Letters, 31, 720-721, (Apr. 1995).

Foster, R., et al., "High Rate Low-Temperature Selective Tungsten", In: Tungsten and Other Refractory Metals for VLSI Applications III, V.A. Wells, ed., Materials Res. Soc., Pittsburgh, PA, 69-72, (1988).

Gong, S., et al., "Techniques for Reducing Switching Noise in High Speed Digital Systems", Proceedings of the 8th Annual IEEE International ASIC Conference and Exhibit, 21-24 (1995).

Heavens, O., Optical Properties of Thin Solid Films, Dover Pubs. Inc., New York, 167, (1965).

Horie, H., et al., "Novel High Aspect Ratio Aluminum Plug for Logic/DRAM LSI's Using Polysilicon-Aluminum Substitute", Technical Digest: IEEE Int. Electron Devices Meeting, San Francisco, CA, 946-948, (1996).

Kim, Y.S., et al., "A Study on Pyrolysis DMEAA for Selective Deposition of Aluminum", In: Advanced Metallization and Interconnect Systems for ULSI Applications in 1995, R.C. Ellwanger, et al., (eds.), Materials Research Society, Pittsburgh, PA, 675-680, (1996).

Klaus, et al., "Atomic Layer Controlled Growth of SiO2 Films Using Binary Reaction Sequence Chemistry", Applied Physics Lett. 70(9), 1092-94, (Mar. 3, 1997).

Lehmann, et al., "A Novel Capacitor Technology Based on Porous Silicon", Thin Solid Films 276, Elsevier Science, 138-42, (1996).

Lehmann, V., "The Physics of Macropore Formation in Low Doped n-Type Silicon", J. Electrochem. Soc., 140, 2836-2843, (Oct. 1993).

Masu, K., et al., "Multilevel Metallization Based on Al CVD", 1996 IEEE Symposium on VLSI Technology, Digest of Technical Papers, Honolulu, HI, 44-45, (Jun. 11-13, 1996).

McCredie, B.D., et al., "Modeling, Measurement, and Simulation of Simultaneous Switching Noise", IEEE Transactions on Components, Packaging, and Manufacturing Technology--Part B, 19, 461-472, (Aug. 1996).

Muller, K., et al., "Trench Storage Node Technology for Gigabit DRAM Generations", Digest IEEE Int. Electron Devices Meeting, San Francisco, CA, 594-597, (Dec. 1996).

Ohba, T., et al., "Evaluation on Selective Deposition of CVD W Films by Measurement of Surface Temperature", In: Tungsten and Other Refractory Metals for VLSI Applications II, Materials Research Society, Pittsburgh, PA, 59-66, (1987).

Ohba, T., et al., "Selective Chemical Vapor Deposition of Tungsten Using Silane and Polysilane Reductions", In: Tungsten and Other Refractory Metals for VLSI Applications IV, Materials Research Society, Pittsburgh, PA, 17-25, (1989).

Ott, A.W., et al., "Al303 Thin Film Growth on Si (100) Using Binary Reaction Sequence Chemistry", Thin Solid Films, vol. 292, 135-44, (1997).

Ramo, S., et al., Fields and Waves in Communication Electronics, John Wiley & Sons, Inc., New York, 428-433, (1993).

Senthinathan, R., et al., "Reference Plane Parasitics Modeling and Their Contribution to the Power and Ground Path "Effective" Inductance as Seen by the Output Drivers", IEEE Transactions on Microwave Theory and Techniques, 42, 1765-1773, (Sep. 1994).

Stanisic, B.R., et al., "Addressing Noise Decoupling in Mixed-Signal IC's: Power Distribution Design and Cell Customization", IEEE Journal of Solid-State Circuits, 30, 321-236, (Mar. 1995).

Suntola, T., "Atomic Layer Epitaxy", Handbook of Crystal Growth 3, Thin Films of Epitaxy, Part B: Growth Mechanics and Dynamics, Elsevier, Amsterdam, 601-63, (1994).

Sze, S.M., VLSI Technology, 2nd Edition, Mc Graw-Hill, NY, 90, (1988).

Vittal, A., et al., "Clock Skew Optimization for Ground Bounce Control", 1996 IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, San Jose, CA, 395-399, (Nov. 10-14, 1996).

Wooley, et al., "Experimental Results and Modeling Techniques for Substrate Noise in Mixed Signal Integrated Circuits", IEEE Journal of Solid State Circuits, vol. SC-28, 420-30, (1993).


Primary Examiner: Chaudhuri; Olik
Assistant Examiner: Eaton; Kurt
Attorney, Agent or Firm: Schwegman, Lundberg, Woessner & Kluth, P.A.
22 Claims, 11 Drawing Figures

[Previous Patent] [Next Patent] [Back to List]
(2 of 59)