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United States Patent 6,150,687
Noble, et. al. Nov. 21, 2000

Memory cell having a vertical transistor with buried source/drain and dual gates

Abstract

An integrated circuit and fabrication method includes a memory cell for a dynamic random access memory (DRAM). Vertically oriented access transistors are formed on semiconductor pillars on buried bit lines. Buried first and second gates are provided for each access transistor on opposing sides of the pillars. Buried word lines extend in trenches orthogonal to the bit lines. The buried word lines interconnect ones of the first and second gates. In one embodiment, unitary gates are interposed and shared between adjacent pillars for gating the transistors therein. In another embodiment, separate split gates are interposed between and provided to the adjacent pillars for separately gating the transistors therein. In one embodiment, the memory cell has a surface area that is approximately 4 F(^2), where F is a minimum feature size. Bulk-semiconductor and semiconductor-on-insulator (SOI) embodiments are provided.


Inventors: Noble; Wendell P. (Milton, VT); Forbes; Leonard (Corvallis, OR); Ahn; Kie Y. (Chappaqua, NY).
Assignee: Micron Technology, Inc. (Boise, ID).
Appl. No.: 889,462
Filed: Jul. 8, 1997
Intl. Cl. : H01L 27/108
Current U.S. Cl.: 257/302; 257/330
Field of Search: 257/302, 296, 304, 347, 330, 331, 332

References Cited | [Referenced By]

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Primary Examiner: Crane; Sara
Attorney, Agent or Firm: Schwegman, Lundberg, Woessner & Kluth, P.A.
24 Claims, 24 Drawing Figures

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