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United States Patent 6,153,468
Forbes, et. al. Nov. 28, 2000

Method of forming a logic array for a decoder


A programmable memory address decode array with vertical transistors having single or split control lines is used to select only functional lines in a memory array. The transistor is a field-effect transistor (FET) having an electrically isolated (floating) gate that controls electrical conduction between source regions and drain regions. If a particular floating gate is charged with stored electrons, then the transistor will not turn on and will act as the absence of a transistor at this location in a logic array within the decoder. The decoder is programmed at memory test to select an output line responsive to the bits received via the address input lines. A logic array includes densely packed logic cells, each logic cell having a semiconductor pillar providing shared source and drain regions for two vertical floating gate transistors that have individual floating gates and control lines distributed on opposing sides of the pillar. The control lines are formed together with interconnecting address input lines. The source regions share a common ground while the drain regions are connected to the output lines. Both bulk semiconductor and silicon-on-insulator embodiments are provided. If a floating gate transistor is used to represent a logic function, an area of only 2F(^2) is needed per bit of logic, where F is the minimum lithographic feature size.

Inventors: Forbes; Leonard (Corvallis, OR); Noble; Wendell P. (Milton, VT).
Assignee: Micron Technololgy, Inc. (Boise, ID).
Appl. No.: 313,049
Filed: May 17, 1999

Related U.S. Application Data
Division of Ser No. 31,621, Feb. 27, 1998, Pat. No. 5,991,225.
Intl. Cl. : H01L 21/336, H01L 21/84
Current U.S. Cl.: 438/257; 438/157; 438/268; 438/269
Field of Search: 438/257, 268, 269, 157, 193; 365/230.06, 185.01; 257/328, 365, 329, 330, 331

References Cited | [Referenced By]

U.S. Patent Documents
4,604,162Aug., 1986Sobczak 156/657
4,663,831May, 1987Birrittella et al. 129/576.E
4,716,314Dec., 1987Mulder et al. 307/477
4,845,537Jul., 1989Nishimura et al. 357/23.4
4,920,065Apr., 1990Chin et al. 437/52
4,949,138Aug., 1990Nishimura 357/23.6
4,958,318Sept., 1990Harari 365/149
4,965,651Oct., 1990Wagner 357/42
5,001,526Mar., 1991Gotou 357/23.6
5,006,909Apr., 1991Kosa 357/23.6
5,010,386Apr., 1991Groover, III 357/42
5,083,047Jan., 1992Horie et al. 307/465
5,087,581Feb., 1992Rodder 437/41
5,102,817Apr., 1992Chatterjee et al. 437/47
5,177,576Jan., 1993Kimura et al. 257/71
5,208,657May, 1993Chatterjee et al. 257/302
5,221,867Jun., 1993Mitra et al. 307/465
5,376,575Dec., 1994Kim et al. 437/52
5,414,287May, 1995Hong 257/316
5,416,350May, 1995Watanabe 257/330
5,432,739Jul., 1995Pein 365/185
5,460,988Oct., 1995Hong 437/43
5,466,625Nov., 1995Hsieh et al. 437/52
5,497,017Mar., 1996Gonzales 257/306
5,504,357Apr., 1996Kim et al. 257/306
5,519,236May, 1996Ozaki 257/302
5,528,062Jun., 1996Hsieh et al. 257/298
5,563,083Oct., 1996Pein 437/43
5,574,299Nov., 1996Kim 257/296
5,637,898Jun., 1997Baliga 257/330
5,674,769Oct., 1997Alsmeier et al. 437/52
5,705,415Jan., 1998Orlowski et al. 437/43
5,753,947May, 1998Gonzalez 257/296
5,818,084Oct., 1998Williams et al. 257/329
5,827,765Oct., 1998Stengl et al. 438/243
5,907,170May, 1999Forbes et al. 257/296
5,909,618Jun., 1999Forbes et al. 438/242
5,914,511Jun., 1999Noble et al. 257/302
5,920,088Jul., 1999Augusto 257/192
5,936,274Aug., 1999Forbes et al. 257/315
5,963,469Oct., 1999Forbes 365/149
5,973,352Oct., 1999Noble 257/315
5,973,356Oct., 1999Noble et al. 257/319
5,991,225Nov., 1999Forbes et al. 365/230.06
6,025,225Feb., 2000Forbes et al. 438/243
6,043,527Mar., 2000Forbes 257/296
6,066,869May, 2000Noble et al. 257/296
6,081,449Jun., 2000Sekariapuram et al. 365/185.05

Other References

Asai, S., et al., "Technology Challenges for Integration Near and Below 0.1 micrometer", Proceedings of the IEEE, 85, Special Issue on Nanometer-Scale Science & Technology, 505-520, (Apr. 1997).

Bomchil, G., et al., "Porous Silicon: The Material and its Applications in Silicon-On-Insulator Technologies", Applied Surface Science, 41/42, 604-613, (1989).

Hisamoto, D., et al., "A New Stacked Cell Structure for Giga-Bit DRAMs using Vertical Ultra-Thin SOI (DELTA) MOSFETs", 1991 IEEE International Electron Devices Meeting, Technical Digest, Washington, D.C., 959-961, (Dec. 8-11, 1991).

Kang, H.K., et al., "Highly Manufacturable Process Technology for Reliable 256 Mbit and 1Gbit DRAMs", IEEE International Electron Devices Meeting, Technical Digest, San Francisco, CA, 635-638, (Dec. 11-14, 1994).

Maeda, S., et al., "A Vertical Phi-Shape Transistor (VPhiT) Cell for 1 Gbit DRAM and Beyond", 1994 Symposium of VLSI Technology, Digest of Technical Papers, Honolulu, HI, 133-134, (Jun. 7-9, 1994).

Maeda, S., et al., "Impact of a Vertical Phi-Shape Transistor (VPhiT) Cell for 1 Gbit DRAM and Beyond", IEEE Transactions on Electron Devices, 42, 2117-2123, (Dec. 1995).

Pein, H.B., et al., "Performance of the 3-D Sidewall Flash EPROM Cell", IEEE International Electron Devices Meeting, Technical Digest, 11-14, (1993).

Primary Examiner: Smith; Matthew
Assistant Examiner: Malsawma; Lex H.
Attorney, Agent or Firm: Schwegman, Lundberg, Woessner & Kluth, P.A.
18 Claims, 20 Drawing Figures

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