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United States Patent 6,156,374
Forbes, et. al. Dec. 5, 2000

Method of forming insulating material between components of an integrated circuit

Abstract

The invention includes a method of forming an insulating material between components of an integrated circuit. A pair of spaced electrical components are provided over a substrate. Polysilicon is chemical vapor deposited over, between, and against the pair of electrical components. Cavities are formed within the polysilicon to enhance porosity of the polysilicon. After the cavities are formed, at least some of the polysilicon is transformed into porous silicon dioxide.


Inventors: Forbes; Leonard (Corvallis, OR); Ahn; Kie Y. (Chappaqua, NY).
Assignee: Micron Technology, Inc. (Boise, ID).
Appl. No.: 271,058
Filed: Mar. 16, 1999

Related U.S. Application Data
Division of Ser No. 948,372, Oct. 9, 1997.
Intl. Cl. : B05D 5/12, H01L 21/76
Current U.S. Cl.: 427/97; 427/344; 427/387; 427/419.2; 438/409; 438/623; 438/787; 438/960
Field of Search: 438/787, 790, 960, 97; 427/96, 344, 387, 419.2, 431, 623

References Cited | [Referenced By]

U.S. Patent Documents
3,919,060Nov., 1975Pogge et al.
3,954,523May, 1976Magdo et al. 148/175
3,979,230Sept., 1976Anthony et al.
3,998,662Dec., 1976Anthony et al.
4,063,901Dec., 1977Shiba 29/578
4,180,416Dec., 1979Brock 148/1.5
4,561,173Dec., 1985Te Velde
5,023,200Jun., 1991Blewer et al. 437/187
5,103,288Apr., 1992Sakamoto et al.
5,141,896Aug., 1992Katoh
5,171,713Dec., 1992Matthews
5,461,003Oct., 1995Havemann et al.
5,470,801Nov., 1995Kapoor et al. 437/238
5,488,015Jan., 1996Havermann et al. 437/195
5,496,773Mar., 1996Rhodes et al.
5,525,857Jun., 1996Gnade et al.
5,527,737Jun., 1996Jeng 437/195
5,554,567Sept., 1996Wang
5,583,078Dec., 1996Osenbach
5,599,745Feb., 1997Reinberg
5,629,238May, 1997Choi et al.
5,670,828Sept., 1997Cheung et al.
5,691,565Nov., 1997Manning
5,691,573Nov., 1997Avanzino et al.
5,736,425Apr., 1998Smith et al.
5,744,399Apr., 1998Rostoker et al.
5,773,363Jun., 1998Derderian et al.
5,804,508Sept., 1998Gnade et al.
5,807,607Sept., 1998Smith et al.
5,861,345Jan., 1999Chou et al.
5,882,978Mar., 1999Srinivasan et al.
5,883,014Mar., 1999Chen et al.
5,950,102Sept., 1999Lee
6,001,747Dec., 1999Annapragada
6,028,015Feb., 2000Wang et al.

Other References

Anderson, R.C. et al., "porous Polycrystalline Silicon: A new material for MEMS:", Jnl. of Microelectromechanical Systems, vol. 3, No. 1, pp. 10-18, Mar. 1994.

Abstract: Anderson, R.C. et al., "Porous Polycrystalline Silicon: A New Material For MEMS", Jnl. of Microelectromechanical Systems (Mar. 1994), vol. 3, No. 1, pp. 10-18.

Anderson, R.C. et al., "Porous polycrystalline silicon: A new material for MEMS", Journal of Microelectromechanical Systems, vol. 3, No. 1, pp. 10-18.

Togo, M., "A Gate-side Air-gap Structure (GAS) to Reduce the Parasitic Capacitance in MOSFETs", 1996 Sympos. on VLSI Technology Digest of Technical Papers, IEEE 1996, pp. 38-39.

Anand, M.B., "NURA: A Feasible, Gas-Dielectric Interconnect Process", 1996 Sympos. on VLSI Technology Digest of Technical Papers, IEEE 1996, pp 82-83.

Watanabe, H., "A Novel Stacked Capacitor with Porous-Si Electrodes for High Density DRAMs", Microelectronics Research Laboratories, NEC Corp., date unknown, pp. 17-18.

Homma, Tetsuya, "Low Dielectric Constant Materials and Methods for Interlayer Dielectric Films in Ultralarge-Scale Integrated Circuit Multilevel Interconnections", Materials Science & Engineering., R23, pp. 243-285 (1998).

Abstract: Townsend, P.H., et al., "SiLK Polymer Coating With Low Dielectric Constant and High Thermal Stability for ULSI Interlayer Dielectric", The Dow Chemical Company, Midland, MI, 9 Pages, (Undated).

Product Brochure and Material Safety Data Sheet, "Interlayer Dielectric", JSR Microelectronics, 12 Pages (1997) No Month.

U.S. application No. 08/947,847, Juengling et al., filed Oct. 9, 1997.

Singer, Peter, "The New Low-k Candidate: It's a Gas", (Technology News/Wafer Processing) Semiconductor International, 1 Page, (Mar. 1989).


Primary Examiner: Talbot; Brian K.
Attorney, Agent or Firm: Wells, St. John, Roberts, Gregory & Matkin
6 Claims, 5 Drawing Figures

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