[Help]Full Text[Boolean Search][Advanced][Number Search][Order Copy][PTDLs]

[Previous Patent] [Next Patent] [Back to List]
(3 of 67)

United States Patent 6,165,828
Forbes, et. al. Dec. 26, 2000

Structure and method for gated lateral bipolar transistors


An improved structure and method for gated lateral bipolar transistors is provided. The present invention capitalizes on opposing sidewall structures and adjacent conductive sidewall members to conserve available surface space on the semiconductor chips. The conserved surface space allows a higher density of structures per chip. The conductive sidewall members couple to the gate of the gated lateral bipolar transistor and, additionally, to a retrograded, more highly doped bottom layer. The improved structure provides for both metal-oxide semiconductor (MOS) type conduction and bipolar junction transistor (BJT) type conduction beneath the gate of the gated lateral bipolar transistor.

Inventors: Forbes; Leonard (Corvallis, OR); Noble; Wendell P. (Milton, VT).
Assignee: Micron Technology, Inc. (Boise, ID).
Appl. No.: 144,811
Filed: Sept. 1, 1998

Related U.S. Application Data
Division of Ser No. 50,266, Mar. 30, 1998, Pat. No. 6,075,272.
Intl. Cl. : H01L 21/8249
Current U.S. Cl.: 438/234; 438/309; 438/348; 438/351
Field of Search: 438/308, 309, 267, 202, 234, 235, 236, 351, 348

References Cited | [Referenced By]

U.S. Patent Documents
4,450,048May, 1984Gaulier 204/15
4,673,962Jun., 1987Chatterjee et al. 357/23.6
4,922,315May, 1990Vu 257/507
4,987,089Jan., 1991Roberts 437/34
4,996,574Feb., 1991Shirasaki 357/23.7
5,006,909Apr., 1991Kosa 357/23.6
5,023,688Jun., 1991Ando et al. 357/42
5,097,381Mar., 1992Vo et al. 361/313
5,122,848Jun., 1992Lee et al. 357/23.6
5,250,450Oct., 1993Lee et al. 437/40
5,315,143May, 1994Tsuji 257/351
5,350,934Sept., 1994Matsuda 257/139
5,379,255Jan., 1995Shah 438/267
5,453,636Sept., 1995Eitan et al. 257/378
5,491,356Feb., 1996Dennison et al. 257/306
5,508,544Apr., 1996Shah 257/316
5,528,062Jun., 1996Hsieh et al. 257/298
5,541,432Jul., 1996Tsuji 257/350
5,554,870Sept., 1996Fitch et al. 257/334
5,581,104Dec., 1996Lowrey et al.
5,585,998Dec., 1996Kotecki et al. 361/321.4
5,587,665Dec., 1996Jiang 326/16
5,646,900Jul., 1997Tsukude et al. 365/205
5,680,345Oct., 1997Hsu et al. 365/185.01
5,689,121Nov., 1997Kitagawa et al. 257/139
5,691,230Nov., 1997Forbes 437/62
5,796,143Aug., 1998Fulford, Jr. et al. 257/330
5,796,166Aug., 1998Agnello et al. 257/751
5,892,260Apr., 1999Okumura et al. 257/347
5,907,170May, 1999Forbes et al. 257/296
5,909,618Jun., 1999Forbes et al. 438/242
5,914,511Jun., 1999Noble et al. 257/302
5,936,274Aug., 1999Forbes et al. 257/315
5,973,356Oct., 1999Noble et al. 257/319

Foreign Patent Documents
000431855B1Jul., 1995EP
Other References

Yilmaz et al.; "Recent Advances in Insulated Gate Bipolar Transistor Technology", IEEE Transactions on Industry Applications, vol. 26, No. 5 Sep./Oct. 1990, pp. 831-834.

Wolf, S.; Silicon Processing for the VLSI Era vol. 2: Process Integration, Sunset Beach, CA, 1990, pp. 389-392. No Month.

Horiguchi, et al., "Switched-Source-Impedance CMOS Circuit for Low Standby Subthreshold Current Giga-Scale LSIs", IEEE Journal of Solid State Circuits, vol. 28, 1131-1135, (1993) No Month.

Huang, W.L., et al., "TFSOI Complementary BiCMOS Technology for Low Power Applications", IEEE Transactions on Electron Devices, 42, 506-512, (Mar. 1995).

Jaeger, et al., "A High-speed Sensing Scheme for 1T Dynamic RAMS Utilizing the Clamped Bit-line Sense Amplifier", IEEE Journal of Solid State Circuits, vol. 27, 618-25, (1992) No Month.

Ko, et al., "High-gain Lateral Bipolar Action ina MOSFET Structure", IEEE Trans. on Electron Devices, vol. 38, No. 11, 2487-96, (Nov. 1991).

MacSweeney, D., et al., "Modelling of Lateral Bipolar Devices in a CMOS Process", IEEE Bipolar Circuits and Technology Meeting, Minneapolis, MN, 27-30, (Sep. 1996).

Parke, S.A., et al., "A High-Performance Lateral Bipolar Transistor Fabricated on SIMOX", IEEE Electron Device Letters, 14, 33-35, (Jan. 1993).

Rabaey, Digital Integrated Circuits, Prentice Hall, Englewood Cliffs, NJ, 222-232, (1996) No Month.

Saito, M., et al., "Techniques for Controlling Effective Vth in Multi-Gbit DRAM Sense Amplifier", 1996 Symposium on VLSI Circuits, Digest of Technical Papers, Honolulu, HI, 106-107, (Jun. 13-15, 1996).

Seevinck, E., et al., "Current-Mode Techniques for High-Speed VLSI Circuits with Application to Current Sense Amplifier for CMOS SRAM's", IEEE Journal of Solid-State Circuits, 26, 525-536, (Apr. 1991).

Shimomura, K., et al., "A 1V 46ns 16Mb SOI-DRAM with Body Control Technique", 1997 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 68-69, (Feb. 6, 1997).

Tsui, P.G., et al., "A Versatile Half-Micron Complementary BiCMOS Technology for Microprocessor-Based Smart Power Applications", IEEE Transactions on Electron Devices, 42, 564-570, (Mar. 1995).

Tuinega, A Guide to Circuit Simulation and Analysis Using PSPICE, Prentice Hall, Englewood Cliffs, NJ, (1988) No Month.

Wong, et al., "A 1V CMOS Digital Circuits with Double-Gate Driven MOSFET", IEEE Int. Solid State Circuits Conference, San Francisco, 292-93, (1997) No Month.

Chen, M.J., et al., "Back-Gate Forward Bias Method for Low-Voltage CMOS Digital Cicuits", IEEE Transactions on Electron Devices, 43, 904-909, (Jun. 1986).

Chen, M.J., et al., "Optimizing the Match in Weakly Inverted MOSFET's by Gated Lateral Bipolar Action", IEEE Transactions on Electron Devices, 43, 766-773, (May 1996).

Chung, I.Y., et al., "A New SOI Inverter for Low Power Applications", Proceedings of the 1996 IEEE International SOI Conference, Sanibel Island, FL, 20-21, (Sep. 30-Oct. 3, 1996).

Denton, J.P., et al., "Fully Depleted Dual-Gated Thin-Film SOI P-MOSFET's Fabricated in SOI Islands with an Isolated Buried Polysilicon Backgate", IEEE Electron Device Letters, 17, 509-511, (Nov. 1996).

Fuse, T., et al., "A 0.5V 200MHz 1-Stage 32b ALU Using a Body Bias Controlled SOI Pass-Gate Logic", 1997 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 286-287, (1997) No Month.

Holman, W.T., et al., "A Compact Low Noise Operational Amplifier for a 1.2 Micrometer Digital CMOS Technology", IEEE Journal of Solid-State Circuits, 30, 710-714, (Jun. 1995).

Primary Examiner: Niebling; John F.
Assistant Examiner: Lattin; Christopher
Attorney, Agent or Firm: Schwegman, Lundberg, Woessner & Kluth, P.A.
20 Claims, 14 Drawing Figures

[Previous Patent] [Next Patent] [Back to List]
(3 of 67)