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United States Patent 6,165,836
Forbes, et. al. Dec. 26, 2000

Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor

Abstract

A memory cell. The memory cell includes an access transistor. The access transistor is formed in a pillar of single crystal semiconductor material. The transistor has first and second source/drain regions and a body region that are vertically aligned. The memory cell also includes a body contact that is coupled to the body region. A gate of the transistor is disposed on a side of the pillar that is opposite from the body contact. A trench capacitor is also included. The trench capacitor includes a first plate that is formed integral with the first source/drain region of the access transistor and a second plate that is disposed adjacent to the first plate and separated from the first plate by a gate oxide. An insulator layer that separates the access transistor and the trench capacitor from an underlying layer of semiconductor material.


Inventors: Forbes; Leonard (Corvallis, OR); Noble; Wendell P. (Milton, VT).
Assignee: Micron Technology, Inc. (Boise, ID).
Appl. No.: 138,794
Filed: Aug. 24, 1998

Related U.S. Application Data
Division of Ser No. 939,732, Oct. 6, 1997, Pat. No. 5,907,170.
Intl. Cl. : H01L 21/8242
Current U.S. Cl.: 438/243; 438/587
Field of Search: 438/243, 244, 246, 247, 248, 386, 387, 389, 587, 588

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Primary Examiner: Chaudhari; Chandra
Attorney, Agent or Firm: Schwegman, Lundberg, Woessner & Kluth, P.A.
4 Claims, 19 Drawing Figures

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