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|United States Patent||6,316,969|
|Forbes ,   et al.||November 13, 2001|
Differential receiver having a pair of cross coupled amplifiers improves signal detection in CMOS circuits. Each amplifier includes a first transistor of a first conductivity type and a second transistor of a second conductivity type. A signal input node is coupled to a source region for the first transistor. A signal output node is coupled to drain regions for the first transistor and the second transistor. The differential receiver further includes a third transistor of a first conductivity type. The signal input node for each amplifier is coupled to a gate of the third transistor of the respective amplifier. A drain region of this third transistor is coupled to a positive voltage supply and a source region is coupled to a low voltage potential. The drain region of the third transistor is also coupled to the gate of the first transistor of the respective amplifier. Methods of operation and methods of forming the differential receiver include designing the receiver for current signaling to better impedance match high speed low impedance transmission lines. The novel receiver employs feedback driven by a transmission line coupled to the receiver's input to decrease the input impedance of the receiver. The receiver can match the low impedance of transmission lines while keeping the sizes of devices small and the power dissipation low. In this manner, the receiver facilitates the transmission of high speed signals over long distances with minimal ringing, reflections, noise and cross talk in integrated circuit interconnections.
|Inventors:||Forbes; Leonard (Corvallis, OR); Ahn; Kie Y. (Chappaqua, NY)|
|Assignee:||Micron Technology, Inc. (Boise, ID)|
|Filed:||February 26, 1999|
|Current U.S. Class:||327/55; 327/57; 327/210; 326/30|
|Intern'l Class:||H03H 007/38; H03K 019/018.5; H03K 003/356|
|Field of Search:||327/52,54,55,57,65,67,199,208,210 333/17.3 365/207,208 326/30|
|4180786||Dec., 1979||Forward et al.||327/310.|
|4616148||Oct., 1986||Ochii et al.||327/55.|
|5329190||Jul., 1994||Igarashi et al.||327/50.|
|5357211||Oct., 1994||Bryson et al.||327/108.|
Blalock, T.N., et al., "A High-Speed Sensing Scheme for 1T Dynamic RAM's Utilizing the Clamped Bit-Line Sense Amplifier", IEEE Journal of Solid-State Circuits, 27(4), 618-625, (Apr. 1992).
Blennemann, H., et al., "Off-Chip 400 MBPS Signal Transmission: Noise Reduction Using Non-Resonant Lengths and Other Techiques", Proceedings of the IEEE Multi-Chip Module Conference, pp. 138-142, (1996).
Emeigh, R., et al., "Fully Integrated LVD Clock Generation/Distribution IC", IEEE Custom Integrated Circuits Conference, pp. 53-56, (1997).
Fusi, M.A., et al., "Differential Signal Transmission Through BackPlanes and Connectors", Electronic Packaging and Production, 36(3), pp. 27, 28, 30, 32, (1996).
Kushiyama, N., et al., "An Experimental 295 MHz CMOS 4K .times. 256 SRAM Using Bidirectional Read/Write Shared Sense Amps and Self-Timed Pulsed Word-Line Drivers", IEEE Journal of Solid-State Circuits, 30(11), pp. 1286-1290, (Nov. 1995).
Kushiyama, N., et al., "FP 18.3: A 295MHz CMOS 1M (.times.256) Embedded SRAM using Bi-directional Read/Write Shared Sense Amps and Self-Timed Pulsed Word-Line Drivers", IEEE International Solid State Circuits Conference, 3 pages, (1995).
Li, C.S., et al., "Fully Differential Optical Interconnects For High-Speed Digital Systems", IEEE International Conference on Computer Design: VLSI in Computers & Processors, pp. 190-193, (1992).
Olsen, C.M., et al., "Differential Board/Backplane Optical Interconnects for High-Speed Digital Systems Part II: Simulation Results", IEEE Journal of Lightwave Technology, 11(7), pp. 1250-1262, (1993).
Rabaey, J.M., Digital Integrated Circuits--A Design Perspective, Prentice Hall, Upper Saddle River, New Jersey, pp. 482-493, (1996).
Seevinck, E., et al., "Current-Mode Techniques for High-Speed VLSI Circuits with Application to Current Sense Amplifier for CMOS SRAM's", Journal of Solid State Circuits, 26(4), 525-535, (Apr. 1991).