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|United States Patent||6,320,222|
|Forbes ,   et al.||November 20, 2001|
An improved method and structure are provided for MOSFETs which reduce or eliminate the effects of statistical dopant fluctuations. The device includes a dual-gated FET which can be fabricated using current CMOS processing tools and process steps. The dual-gated MOSFET that has two gates one on each side of a thin fully depleted silicon structure. The silicon film between the two gates is very thin so the device can be fully depleted. In addition, the new device desirably provided improved performance regardless of channel length variations. The method and structure offer a future generation of sub-0.5 .mu.m, uniform, and low threshold voltage (V.sub.t) MOSFETs with an increased range of application, e.g. to include uses in production drivers and clock drivers with uniform characteristics and delays.
|Inventors:||Forbes; Leonard (Corvallis, OR); Noble; Wendell P. (Milton, VT)|
|Assignee:||Micron Technology, Inc. (Boise, ID)|
|Filed:||September 1, 1998|
|Current U.S. Class:||257/331; 257/365|
|Intern'l Class:||H01L 031/113|
|Field of Search:||257/365,328,329,330,331,332|
|5653619||Aug., 1997||Cloud et al.||445/24.|
|5675164||Oct., 1997||Brunner et al.||257/331.|
|5998834||Dec., 1999||Williams et al.||257/330.|
|6060746||May., 2000||Bertin et al.||257/331.|
|Foreign Patent Documents|
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