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United States Patent | 6,383,871 |
Noble ,   et al. | May 7, 2002 |
Improved methods and structures are provided for multiple oxide thicknesses on a single silicon wafer. In particular, improved methods and structures are provided for multiple gate oxide thicknesses on a single chip wherein the chip can include circuitry encompassing a range of technologies including but not limited to the memory and logic technologies. Moreover, these improved methods and structures for multiple oxide thickness on a single silicon wafer can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity. Embodiments of a method for forming a semiconductor device include forming a top layer of SiO.sub.2 on a top surface of a silicon wafer. A trench layer of SiO.sub.2 is also formed on a trench wall of the silicon wafer. The trench wall of the silicon wafer has a different order plane-orientation than the top surface. Additionally, the formation of the top and trench layers of SiO.sub.2 are such that a thickness of the top layer is different from a thickness of the trench layer.
Inventors: | Noble; Wendell P. (Milton, VT); Forbes; Leonard (Corvallis, OR) |
Assignee: | Micron Technology, Inc. (Boise, ID) |
Appl. No.: | 386185 |
Filed: | August 31, 1999 |
Current U.S. Class: | 438/275 |
Intern'l Class: | H01L 021/823.4 |
Field of Search: | 438/275,769,770,198,270 |
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