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|United States Patent||6,384,448|
|Forbes||May 7, 2002|
Structures and methods involving dynamic, "enhancement mode," p-channel flash memories with an ultrathin tunnel oxide thickness, have been provided. Both the write and erase operations are performed by tunneling. According to the teachings of the present invention, the p-channel flash memory cell with thin tunnel oxides will operate on a dynamic basis. The stored data can be refreshed every few seconds as necessary. However, the write and erase operations will however now be orders of magnitude faster than traditional p-channel flash memory and the cell provides a large gain. The present invention further provides structures and methods for p-channel floating gate transistors which avoid p-channel threshold voltage shifts and achieve source side tunneling erase. The p-channel memory cell structure includes a floating gate separated from a channel region by an oxide layer of less than 50 Angstroms (.ANG.). According to the teachings of the present invention, the floating gate is adapted to hold a charge of the order of 10.sup.-7 Coulombs at for at least 1.0 second at 85 degrees Celsius. The method includes applying a potential of less than 3.0 Volts across the floating gate oxide which is less than 50 Angstroms, in order to add or remove a charge from a floating gate. The method further includes reading the p-channel memory cell by applying a potential to a control gate of the p-channel memory cell of less than 1.0 Volt.
|Inventors:||Forbes; Leonard (Corvallis, OR)|
|Assignee:||Micron Technology, Inc. (Boise, ID)|
|Filed:||February 28, 2000|
|Current U.S. Class:||257/315; 257/316|
|Intern'l Class:||H01L 033/00|
|Field of Search:||257/315,316|
|3882469||May., 1975||Gosney, Jr.||340/173.|
|5768193||Jun., 1998||Lee et al.||365/185.|
|5811865||Sep., 1998||Hodges et al.||257/411.|
|5886368||Mar., 1999||Forbes et al.||257/77.|
|6025627||Feb., 2000||Forbes et al.||257/321.|
|6031263||Feb., 2000||Forbes et al.||257/315.|
|6063668||May., 2000||He et al.||438/264.|
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