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United States Patent 6,434,041
Forbes August 13, 2002

Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device

Abstract

A memory device is described which has an n-channel field effect transistor coupled between a memory cell and a data communication line. An NPN bipolar junction transistor is also coupled between the memory cell and the data communication line in parallel to the n-channel access transistor. A base connection of the NPN bipolar junction transistor is described as coupled to a body of the n-channel access transistor. During operation the n-channel field effect transistor is used for writing data to a memory cell, while the NPN bipolar junction transistor is used for read operations in conjunction with a current sense amplifier circuit. The access transistors are described as fabricated as a single vertical pillar.


Inventors: Forbes; Leonard (Corvallis, OR)
Assignee: Micron Technology, Inc. (Boise, ID)
Appl. No.: 916768
Filed: July 27, 2001

Current U.S. Class: 365/177; 365/149; 365/225.6
Intern'l Class: G11C 011/34
Field of Search: 365/149,177,225.6,189.06


References Cited [Referenced By]

U.S. Patent Documents
3657575Apr., 1972Taniguchi et al.307/304.
3806741Apr., 1974Smith307/304.
3931617Jan., 1976Russell340/173.
4051354Sep., 1977Choate235/312.
4604162Aug., 1986Sobczak156/657.
4663831May., 1987Birrittella et al.29/576.
4673962Jun., 1987Chatterjee et al.357/23.
4677589Jun., 1987Haskell et al.365/149.
4761768Aug., 1988Turner et al.365/201.
4766569Aug., 1988Turner et al.365/185.
4920065Apr., 1990Chin et al.437/52.
4958318Sep., 1990Harari365/149.
4987089Jan., 1991Roberts437/34.
5001526Mar., 1991Gotou357/23.
5006909Apr., 1991Kosa357/23.
5017504May., 1991Nishimura et al.437/40.
5021355Jun., 1991Dhong et al.437/35.
5028977Jul., 1991Kenneth et al.357/43.
5057896Oct., 1991Gotou357/49.
5072269Dec., 1991Hieda357/23.
5102817Apr., 1992Chatterjee et al.437/47.
5110752May., 1992Lu437/47.
5128831Jul., 1992Fox, III et al.361/396.
5140388Aug., 1992Bartelink357/23.
5156987Oct., 1992Sandhu et al.437/40.
5177028Jan., 1993Manning437/41.
5177576Jan., 1993Kimura et al.257/71.
5202278Apr., 1993Mathews et al.437/47.
5208657May., 1993Chatterjee et al.257/302.
5216266Jun., 1993Ozaki257/302.
5223081Jun., 1993Doan156/628.
5266514Nov., 1993Tuan et al.437/52.
5292676Mar., 1994Manning437/46.
5316962May., 1994Matsuo et al.437/52.
5320880Jun., 1994Sandhu et al.427/578.
5327380Jul., 1994Kersh, III et al.365/195.
5329481Jul., 1994Seevinck et al.365/177.
5341331Aug., 1994Jeon365/189.
5363325Nov., 1994Sunouchi et al.365/149.
5376575Dec., 1994Kim et al.437/52.
5385854Jan., 1995Batra et al.437/41.
5391911Feb., 1995Beyer et al.257/522.
5392245Feb., 1995Manning365/200.
5393704Feb., 1995Huang et al.437/203.
5396093Mar., 1995Lu257/306.
5409563Apr., 1995Cathey156/643.
5410169Apr., 1995Yamamoto et al.257/301.
5414287May., 1995Hong257/316.
5416350May., 1995Watanabe257/330.
5422499Jun., 1995Manning257/67.
5427972Jun., 1995Shimizu et al.437/52.
5432739Jul., 1995Pein365/185.
5438009Aug., 1995Yang et al.437/52.
5440158Aug., 1995Sung-Mu257/314.
5445986Aug., 1995Hirota437/60.
5451889Sep., 1995Heim et al.326/81.
5460316Oct., 1995Hefele228/39.
5460988Oct., 1995Hong437/43.
5466625Nov., 1995Hsieh et al.437/52.
5483094Jan., 1996Sharma et al.257/316.
5483487Jan., 1996Sung-Mu365/185.
5492853Feb., 1996Jeng et al.437/60.
5495441Feb., 1996Hong365/185.
5497017Mar., 1996Gonzales257/306.
5502629Mar., 1996Ito et al.363/60.
5504357Apr., 1996Kim et al.257/306.
5508219Apr., 1996Bronner et al.437/52.
5508542Apr., 1996Geiss et al.257/301.
5519236May., 1996Ozaki257/302.
5528062Jun., 1996Hsieh et al.257/298.
5563083Oct., 1996Pein437/43.
5574299Nov., 1996Kim257/296.
5593912Jan., 1997Rajeevakumar437/52.
5616934Apr., 1997Dennison et al.257/67.
5640342Jun., 1997Gonzalez365/156.
5641545Jun., 1997Sandhu427/573.
5644540Jul., 1997Manning365/200.
5646900Jul., 1997Tsukude et al.365/205.
5691230Nov., 1997Forbes437/62.
5705415Jan., 1998Orlowski et al.437/43.
5707885Jan., 1998Lim437/52.
5714793Feb., 1998Cartagena et al.257/507.
5789967Aug., 1998Katoh327/408.
5821796Oct., 1998Yaklin et al.327/313.
5834814Nov., 1998Ito257/378.
5852375Dec., 1998Byrne et al.327/108.
5907170May., 1999Forbes et al.257/296.
5909400Jun., 1999Berllin et al.365/187.
5926412Jul., 1999Evans, Jr. et al.365/145.
5946472Aug., 1999Graves et al.395/500.
5991225Nov., 1999Forbes et al.365/230.
5998820Dec., 1999Chi257/296.
6006166Dec., 1999Meyer702/119.
6025225Feb., 2000Forbes et al.438/243.
6043527Mar., 2000Forbes257/296.
6066869May., 2000Noble et al.257/296.
6072209Jun., 2000Noble et al.257/296.
6172535Jan., 2001Hopkins327/66.
6181121Jan., 2001Kirkland et al.323/313.
6181196Jan., 2001Nguyen327/539.
6323719Nov., 2001Chang et al.327/478.
Foreign Patent Documents
63-066963Mar., 1988JP.


Other References

Adler, E., et al., "The Evolution of IBM CMOS DRAM Technology", IBM J. Res. Develop., 39(1/2), 167-188, (1995).
Asai, S., et al., "Technology Challenges for Integration Near and Below 0.1 micrometer", Proceedings of the IEEE, 85(4), Special Issue on Nanometer-Scale Science & Technology, 505-520, (Apr. 1997).
Askin, H.O., et al., "Fet Device Parameters Compensation Circuit", IBM Technical Disclosure Bulletin, 14, 2088-2089, (Dec. 1971).
Banerjee, S.K., et al., "Characterization of Trench Transistors for 3-D Memories", 1986 Symposium on VLSI Technology, Digest of Technical Papers, San Diego, CA, 79-80, (May 1986).
Blalock, T.N., et al., "A High-Speed Sensing Scheme for 1T Dynamic RAM's Utilizing the Clamped Bit-Line Sense Amplifier", IEEE Journal of Solid-State Circuits, 27(4), pp. 618-624, (Apr. 1992).
Bomchil, G., et al., "Porous Silicon: The Material and its Applications in Silicon-On-Insulator Technologies", Applied Surface Science, 41/42, 604-613, (1989).
Burnett, D., et al., "Implications of Fundametnal Threshold Voltage Variations for High-Density SRAM and Logic Circuits", 1994 Symposium on VLSI Technology, Digest of Technical Papers, Honolulu, HI, 15-16, (Jun. 1994).
Burnett, D., et al., "Statistical Threshold-Voltage Variation and its Impact on Supply-Voltage Scaling", Proceedings SPIE: Microelectronic Device and Multilevel Interconnection Technology, 2636, 83-90, (1995).
Chen, M., et al., "Back-Gate Forward Bias Method for Low Voltage CMOS Digital Cicuits", IEEE Transactions on Electron Devices, 43, 904-909, (1996).
Chen, M.J., et al., "Back-Gate Forward Bias Method for Low-Voltage CMOS Digital Cicuits", IEEE Transactions on Electron Devices, 43, 904-909, (Jun. 1996).
Chen, M.J., et al., "Optimizing the Match in Weakly Inverted MOSFET's by Gated Lateral Bipolar Action", IEEE Transactions on Electron Devices, 43, 766-773, (May 1996).
Chung, I.Y., et al., "A New SOI Inverter for Low Power Applications", Proceedings of the 1996 IEEE International SOI Conference, Sanibel Island, FL, 20-21, (1996).
Clemen, R., et al., "VT-compensated TTL-Compatible Mos Amplifier", IBM Technical Disclosure Bulletin, 21, 2874-2875, (1978).
De, V.K., et al., "Random MOSFET Parameter Fluctuation Limits to Gigascale Integration (GSI)", 1996 Symposium on VLSI Technology, Digest of Technical Papers, Honolulu, HI, 198-199, (Jun. 11-13, 1996).
De, V.K., et al., "Random Mosfet Parameter Fluctuation Limits to Gigascale Integration (GST)", Symposium on VLSI Technology Digest of Technical Papers, 198-199, (1996).
DeBar, D.E., "Dynamic Substrate Bias to Achieve Radiation Hardening", IBM Technical Disclosure Bulletin, 25, 5829-5830, (1983).
Denton, J.P., et al., "Fully Depleted Dual-Gated Thin-Film SOI P-MOSFET's Fabricated in SOI Islands with an Isolated Buried Polysilicon Backgate", IEEE Electron Device Letters, 17(11), 509-511, (Nov. 1996).
Fong, Y., et al., "Oxide Grown on Textured Single-Crystal Silicon--Dependence on Process and Application in EEPROMs", IEEE Transactions on Electron Devices, 37(3), pp. 583-590, (Mar. 1990).
Forbes, L., "Automatic On-clip Threshold Voltage Compensation", IBM Technical Disclosure Bulletin, 14, 2894-2895, (1972).
Forbes, L., et al., "Resonant Forward-Biased Guard-Ring Diodes for Suppression of Substrate Noise in Mixed-Mode CMOS Circuits", Electronics Letters, 31, 720-721, (Apr. 1995).
Foster, R., et al., "High Rate Low-Temperature Selective Tungsten", In: Tungsten and Other Refractory Metals for VLSI Applications III, V.A. Wells, ed., Materials Res. Soc., Pittsburgh, PA, 69-72, (1988).
Frantz, H., et al., "Mosfet Substrate Bias-Voltage Generator", IBM Technical Disclosure Bulletin, 11, 1219-1220, (Mar. 1969).
Fuse, T., et al., "A 0.5V 200MHz 1-Stage 32b ALU Using a Body Bias Controlled SOI Pass-Gate Logic", 1997 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 286-287, (1997).
Gong, S., et al., "Techniques for Reducing Switching Noise in High Speed Digital Systems", Proceedings of the 8th Annual IEEE International ASIC Conference and Exhibit, Austin, TX, 21-24, (1995).
Hao, M.Y., et al., "Electrical Characteristics of Oxynitrides Grown on Textured Single-Crystal Silicon", Appl. Phys. Lett., 60, 445-447, (Jan. 1992).
Harada, M., et al., "Suppression of Threshold Voltage Variation in MTCMOS/SIMOX Circuit Operating Below 0.5 V", 1996 Symposium on VLSI Technology, Digest of Technical Papers, Honolulu, HI, 96-97, (Jun. 11-13, 1996).
Heavens, O., Optical Properties of Thin Solid Films, Dover Pubs. Inc., New York, 155-206, (1965).
Hisamoto, D., et al., "A New Stacked Cell Structure for Giga-Bit DRAMs using Vertical Ultra-Thin SOI (DELTA) MOSFETs", 1991 IEEE International Electron Devices Meeting, Technical Digest, Washington, D.C., 959-961, (Dec. 8-11, 1991).
Hodges, D.A., et al., "MOS Decoders", In: Analysis and Design of Digital Integrated Circuits, 2nd Edition, Section: 9.1.3, 354-357, (1988).
Holman, W.T., et al., "A Compact Low Noise Operational Amplifier for a 1.2 Micrometer Digital CMOS Technology", IEEE Journal of Solid-State Circuits, 30, 710-714, (Jun. 1995).
Horie, H., et al., "Novel High Aspect Ratio Aluminum Plug for Logic/DRAM LSI's Using Polysilicon-Aluminum Substitute", Technical Digest: IEEE International Electron Devices Meeting, San Francisco, CA, 946-948, (1996).
Hu, G., et al., "Will Flash Memory Replace Hard Disk Drive?", 1994 IEEE International Electron Device Meeting, Panel Discussion, Session 24, Outline, 2 pages, (Dec. 1994).
Huang, W.L., et al., "TFSOI Complementary BiCMOS Technology for Low Power Applications", IEEE Transactions on Electron Devices, 42, 506-512, (Mar. 1995).
Jun. Y.K., et al., "The Fabrication and Electrical Properties of Modulated Stacked Capacitor for Advanced DRAM Applications", IEEE Electron Device Letters, 13, 430-432, (Aug. 1992).
Jung, T.S., et al., "A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications", IEEE Journal of Solid-State Circuits, 31, 1575-1583, (Nov. 1996).
Kang, H.K., et al., "Highly Manufacturable Process Technology for Reliable 256 Mbit and 1Gbit DRAMs", IEEE International Electron Devices Meeting, Technical Digest, San Francisco, CA, 635-638, (Dec. 11-14, 1994).
Kim, Y.S., et al., "A Study on Pyrolysis DMEAA for Selective Deposition of Aluminum", In: Advanced Metallization and Interconnect Systems for ULSI Applications in 1995, R.C. Ellwanger, et al., (eds.), Materials Research Society, Pittsburgh, PA, 675-680, (1996).
Kishimoto, T., et al., "Well Structure by High-Energy Boron Implantation for Soft-Error Reduction in Dynamic Random Access Memories (DRAMs)", Japanese Journal of Applied Physics, 34, 6899-6902, (Dec. 1995).
Klaus, et al., "Atomic Layer Controlled Growth of SiO2 Films Using Binary Reaction Sequence Chemistry", Applied Physics Lett. 70(9), 1092-94, (Mar. 3, 1997).
Kohyama, Y., et al., "Buried Bit-Line Cell for 64MB DRAMs", 1990 Symposium on VLSI Technology, Digest of Technical Papers, Honolulu, HI, 17-18, (Jun. 4-7, 1990).
Koshida, N., et al., "Efficient Visible Photoluminescence from Porous Silicon", Japanese Journal of Applied Physics, 30, L1221-L1223, (Jul. 1991).
Kuge, S., et al., "SOI-DRAM Circuits Technologies for Low Power High Speed Multigiga Scale Memories", IEEE Journal of Solid-State Circuits, 31(4), pp. 586-591, (Apr. 1996).
Lantz, II, L., "Soft Errors Induced By Alpha Particles", IEEE Transactions on Reliability, 45, 174-179, (Jun. 1996).
Lehmann, et al., "A Novel Capacitor Technology Based on Porous Silicon", Thin Solid Films 276, Elsevier Science, 138-42, (1996).
Lehmann, V., "The Physics of Macropore Formation in Low Doped n-Type Silicon", Journal of the Electrochemical Society, 140(10), 2836-2843, (Oct. 1993).
Lu, N., et al., "The SPT Cell--A New Substrate-Plate Trench Cell for DRAMs", 1985 IEEE International Electron Devices Meeting, Technical Digest, Washington, D.C., 771-772, (Dec. 1-4, 1985).
MacSweeney, D., et al., "Modelling of Lateral Bipolar Devices in a CMOS Process", IEEE Bipolar Circuits and Technology Meeting, Minneapolis, MN, 27-30, (Sep. 1996).
Maeda, S., et al., "A Vertical Phi-Shape Transistor (VPhiT) Cell for 1 Gbit DRAM and Beyond", 1994 Symposium of VLSI Technology, Digest of Technical Papers, Honolulu, HI, 133-134, (Jun. 7-9, 1994).
Maeda, S., et al., "Impact of a Vertical Phi-Shape Transistor (VPhiT) Cell for 1 Gbit DRAM and Beyond", IEEE Transactions on Electron Devices, 42, 2117-2123, (Dec. 1995).
Malaviya, S., IBM TBD, 15, p. 42, (Jul. 1972).
Masu, K., et al., "Multilevel Metallization Based on Al CVD", 1996 IEEE Symposium on VLSI Technology, Digest of Technical Papers, Honolulu, HI, 44-45, (Jun. 11-13, 1996).
McCredie, B.D., et al., "Modeling, Measurement, and Simulation of Simultaneous Switching Noise", IEEE Transactions on Components, Packaging, and Manufacturing Technology--Part B, 19, 461-472, (Aug. 1996).
Muller, K., et al., "Trench Storage Node Technology for Gigabit DRAM Generations", Digest IEEE International Electron Devices Meeting, San Francisco, CA, 507-510, (Dec. 1996).
Nitayama, A., et al., "High Speed and Compact CMOS Circuits with Multipillar Surrounding Gate Transistors", IEEE Transactions on Electron Devices, 36, 2605-2606, (Nov. 1989).
Ohba, T., et al., "Evaluation on Selective Deposition of CVD W Films by Measurement of Surface Temperature", In: Tungsten and Other Refractory Metals for VLSI Applications II, Materials Research Society, Pittsburgh, PA, 59-66, (1987).
Ohba, T., et al., "Selective Chemical Vapor Deposition of Tungsten Using Silane and Polysilane Reductions", In: Tungsten and Other Refractory Metals for VLSI Applications IV, Materials Research Society, Pittsburgh, PA, 17-25, (1989).
Ohno, Y., et al., "Estimation of the Charge Collection for the Soft-Error Immunity by the 3D-Device Simulation and the Quantitative Investigation", Simulation of Semiconductor Devices and Processes, 6, 302-305, (Sep. 1995).
Oowaki, Y., et al., "New alpha-Particle Induced Soft Error Mechanism in a Three Dimensional Capacitor Cell", IEICE Transactions on Electronics, 78-C, 845-851, (Jul. 1995).
Oshida, S., et al., "Minority Carrier Collection in 256 M-bit DRAM Cell on Incidence of Alpha-Particle Analyzed by Three-Dimensional Device Simulation", IEICE Transactions on Electronics, 76-C, 1604-1610, (Nov. 1993).
Ott, A.W., et al., "Al303 Thin Film Growth on Si(100) Using Binary Reaction Sequence Chemistry", Thin Solid Films, vol. 292, 135-44, (1997).
Ozaki, T., et al., "A Surrounding Isolation-Merged Plate Electrode (Simple) Cell with Checkered Layout for 256Mbit DRAMs and Beyond", 1991 IEEE International Electron Devices Meeting, Washington, D.C., 469-472, (Dec. 8-11, 1991).
Parke, S.A., et al., "A High-Performance Lateral Bipolar Transistor Fabricated on SIMOX", IEEE Electron Device Letters, 14, 33-35, (Jan. 1993).
Pein, H., et al., "A 3-D Sidewall Flash EPROM Cell and Memory Array", IEEE Transactions on Electron Devices, 40, 2126-2127, (Nov. 1993).
Pein, H., et al., "Performance of the 3-D Pencil Flash EPROM Cell and Memory Array", IEEE Transactions on Electron Devices, 42, 1982-1991, (Nov., 1995).
Pein, H.B., et al., "Performance of the 3-D Sidewall Flash EPROM Cell", IEEE International Electron Devices Meeting, Technical Digest, 11-14, (1993).
Puri, Y., "Substrate Voltage Bounce in NMOS Self-biased Substrates", IEEE Journal of Solid-State Circuits, SC-13, 515-519, (Aug. 1978).
Ramo, S., et al., Fields and Waves in Communication Electronics, Third Edition, John Wiley & Sons, Inc., pp. 428-433, (1994).
Rao, K.V., et al., "Trench Capcitor Design Issues in VLSI DRAM Cells", 1986 IEEE International Electron Devices Meeting, Technical Digest, Los Angeles, CA 140-143, (Dec. 7-10, 1986).
Richardson, W.F., et al., "A Trench Transistor Cross-Point DRAM Cell", IEEE International Electron Devices Meeting, Washington, D.C., 714-717, (Dec. 1-4, 1985).
Sagara, K., et al., "A 0.72 micro-meter2 Recessed STC (RSTC) Technology for 256Mbit DRAMs using Quarter-Micron Phase-Shift Lithography", 1992 Symposium on VLSI Technology, Digest of Technical Papers, Seattle, WA, 10-11, (Jun. 2-4, 1992).
Saito, M., et al., "Technique for Controlling Effective Vth in Multi-Gbit DRAM Sense Amplifier", 1996 Symposium on VLSI Circuits, Digest of Technical Papers, Honolulu, HI, 106-107, (Jun. 13-15, 1996).
Seevinck, E., et al., "Current-Mode Techniques for High-Speed VLSI Circuits with Application to Current Sense Amplifier for CMOS SRAM's" IEEE Journal of Solid State Circuits, 26(4), pp. 525-536, (Apr. 1991).
Senthinathan, R., et al., "Reference Plane Parasitics Modeling and Their Contribution to the Power and Ground Path "Effective" Inductance as Seen by the Output Drivers", IEEE Transactions on Microwave Theory and Techniques, 42, 1765-1773, (Sep. 1994).
Shah, A.H., et al., "A 4-Mbit DRAM with Trench-Transistor Cell", IEEE Journal of Solid-State Circuits, SC-21, 618-625, (Oct. 1986).
Shah, A.H., et al., "A 4Mb DRAM with Cross-Point Trench Transistor Cell", 1986 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 268-269, (Feb. 21, 1986).
Sherony, M.J., et al., "Reduction of Threshold Voltage Sensitivity in SOI MOSFET's", IEEE Electron Device Letters, 16, 100-102, (Mar. 1995).
Shimomura, K., et al., "A 1V 46ns 16Mb SOI-DRAM with Body Control Technique", 1997 IEEE International Solid-State Circutis Conference, Digest of Technical Papers, 68-69, (Feb. 6, 1997).
Stanisic, B.R., et al., "Addressing Noise Decoupling in Mixed-Signal IC's: Power Distribution Design and Cell Customization", IEEE Journal of Solid-State Circuits, 30, 321-326, (Mar. 1995).
Stellwag, T.B., et al., "A Vertically-Integrated GaAs Bipolar DRAM Cell", IEEE Transactions on Electron Devices, 38, 2704-2705, (Dec. 1991).
Su, D.K., et al., "Experimental Results and Modeling Techniques for Substrate Noise in Mixed Signal Integrated Circuits", IEEE Journal of Solid State Circuits, vol. SC-28, 420-30, (1993).
Su, D.K., et al., "Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits", IEEE Journal of Solid-State Circuits, 28(4), 420-430, (Apr. 1993).
Suma, K., et al., "An SOI-DRAM with Wide Operating Voltage Range by CMSO/SIMOX Technology", IEEE Journal of Solid-State Circuits, 29(11), pp. 1323-1329, (Nov. 1994).
Sunouchi, K., et al., "A Surrounding Gate Transistor (SGT) Cell for 64/256Mbit DRAMs", 1989 IEEE International Electron Devices Meeting, Technical Digest, Washington, D.C., 23-26, (Dec. 3-6, 1989).
Sunouchi, K., et al., "Process Integration for 64M DRAM Using an Asymmetrical Stacked Trench Capacitor (AST) Cell", 1990 IEEE International Electron Devices Meeting, San Francisco, CA, 647-650, (Dec. 9-12, 1990).
Suntola, T., "Atomic Layer Epitaxy", Handbook of Crystal Growth 3, Thin Films of Epitaxy, Part B: Growth Mechanics and Dynamics, Elsevier, Amsterdam, 601-63, (1994).
Sze, S.M., VLSI Technology, 2nd Edition, Mc Graw-Hill, NY, 90, (1988).
Takai, M., et al., "Direct Measurement and Improvement of Local Soft Error Susceptibility in Dynamic Random Access Memories", Nuclear Instruments & Methods in Physics Research, B-99, 562-565, (Nov. 7-10, 1994).
Takato, H., et al., "High Performance CMOS Surrounding Gate Transistor (SGT) for Ultra High Density LSIs", IEEE International Electron Devices Meeting, Technical Digest, 222-225, (1988).
Takato, H., et al., "Impact of Surrounding Gate Transistor (SGT) for Ultra-High Density LSI's", IEEE Transactions on Electron Devices, 38, 573-578, (Mar. 1991).
Tanabe, N., et al., "A Ferroelectric Capacitor Over Bit-Line (F-COB) Cell for High Density Nonvolatile Ferroelectric Memories", 1995 Symposium on VLSI Technology, Digest of Technical Papers, Kyoto, Japan, 123-124, (Jun. 6-8, 1995).
Temmler, D., "Multilayer Vertical Stacked Capacitors (MVSTC) for 64Mbit and 256Mbit DRAMs", 1991 Symposium on VLSI Technology, Digest of Technical Papers, OPiso, 13-14, (May 28-30, 1991).
Terauchi, M., et al., "A Surrounding Gate Transistor (SGT) Gain Cell for Ultra High Density DRAMs", 1993, Symposium on VLSI Technology, Digest of Technical Papers, Kyoto, Japan, 21-22, (1993).
Tsui, P.G., et al., "A Versatile Half-Micron Complementary BiCMOS Technology for Microprocessor-Based Smart Power Applications", IEEE Transactions on Electron Devices, 42, 564-570, (Mar. 1995).
Verdonckt-Vandebroek, S., et al., "High-Gain Lateral Bipolar Action in a MOSFET Structure", IEEE Transactions on Electron Devices 38, 2487-2496, (Nov. 1991).
Vittal, A., et al., "Clock Skew Optimization for Ground Bounce Control", 1996 IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, San Jose, CA, 395-399, (Nov. 10-14, 1996).
Wang, N., Digital MOS Integrated Circuits, Prentice Hall, Inc. , Englewood Cliffs, NJ, pp. 328-333, (1989).
Wang, P.W., et al., "Excellent Emission Characteristics of Tunneling Oxides Formed Using Ultrathin Silicon Films for Flash Memory Devices" Japanese Journal of Applied Physics, 35, 3369-3373, (Jun. 1996).
Watanabe, H., et al., "A New Cylindrical Capacitor Using Hemispherical Grained Si (HSG-Si) for 256Mb DRAMs", IEEE International Electron Devices Meeting, Technical Digest, San Francisco, CA, 259-262, (Dec. 13-16, 1992).
Watanabe, H., et al., "A Novel Stacked Capacitor with Porous-Si Electrodes for High Density DRAMs", 1993 Symposium on VLSI Technology, Digest of Technical Papers, Kyoto, Japan, 17-18, (1993).
Watanabe, H., et al., "An Advanced Fabrication Technology of Hemispherical Grained (HSG) Poly-Si for High Capacitance Storage Electrodes", Extended Abstracts of the 1991 International Conference on Solid State Devices and Materials, Yokohama, Japan, 478-480, (1991).
Watanabe, H., et al., "Device Application and Structure Observation for Hemispherical-Grained Si", J. Appl. Phys., 71, 3538-3543, (Apr. 1992).
Watanabe, H., et al., "Hemispherical Grained Silicon (HSG-Si) Formation on In-Situ Phosphorous Doped Amorphous-Si Using the Seeding Method", Extended Abstracts of the 1992 International Conference on Solid State Devices and Materials, Tsukuba, Japan, 422-424, (1992).
Watanabe, S., et al., "A Novel Circuit Technology with Surrounding Gate Transistors (SGT's) for Ultra High Density DRAM's" IEEE Journal of Solid-State Circuits, 30, 960-971, (Sep. 1995).
Yamada, T., et al., "A New Cell Structure with a Spread Source/Drain (SSD) MOSFET and a Cylindrical Capacitor for 64-Mb DRAM's", IEEE Transactions on Electron Devices, 38, 2481-2486, (Nov. 1991).
Yamada, T., et al., "Spread Source/Drain (SSD) MOSFET Using Selective Silicon Growth for 64Mbit DRAMs", 1989 IEEE International Electron Devices Meeting, Technical Digest, Washington, D.C., 35-38, (Dec. 3-6, 1989).
Yoshikawa, K., "Impact of Cell Threshold Voltage Distribution in the Array of Flash Memories on Scaled and Multilevel Flash Cell Design", 1996 Symposium on VLSI Technology, Digest of Technical Papers, Honolulu, HI, 240-241, (Jun. 11-13, 1996).

Primary Examiner: Elms; Richard
Assistant Examiner: Nguyen; Hien
Attorney, Agent or Firm: Schwegman, Lundberg, Woessner & Kluth, P.A.

Parent Case Text



RELATED APPLICATIONS

This application is a divisional of U.S. Ser. No. 09/498,433 filed Feb. 4, 2000 which is a divisional of U.S. Ser. No. 09/060,048 filed Apr. 14, 1998. Now a U.S. Pat. No. 6,043,527.

This application is related to the following, commonly assigned applications which are incorporated by reference:

U.S. application Ser. No. 09/028,249 entitled "VERTICAL BIPOLAR READ ACCESS FOR LOW VOLTAGE MEMORY CELL," now a U.S. Pat. No. 5,963,469,

U.S. application Ser. No. 08/944,312 entitled "CIRCUIT AND METHOD FOR A FOLDED BIT LINE MEMORY USING TRENCH PLATE CAPACITOR CELLS WITH BODY BIAS CONTACTS," now a U.S. Pat. No. 5,914,511,

U.S. application Ser. No. 08/939,732, entitled "CIRCUIT AND METHOD FOR AN OPEN BIT LINE MEMORY CELL WITH A VERTICAL TRANSISTOR AND TRENCH PLATE TRENCH CAPACITOR," now a U.S. Pat. No. 5,907,170,

U.S. application Ser. No. 08/939,742, entitled "CIRCUIT AND METHOD FOR A FOLDED BIT LINE MEMORY CELL WITH VERTICAL TRANSISTOR AND TRENCH CAPACITOR," now a U.S. Pat. No. 6,066,869, and

U.S. application Ser. No. 08/944,890, entitled "CIRCUIT AND METHOD FOR AN OPEN BIT LINE MEMORY CELL WITH A VERTICAL TRANSISTOR AND TRENCH PLATE TRENCH CAPACITOR."
Claims



What is claimed is:

1. A method of storing data in a memory device, the method comprising:

detecting current signals from an input device using a current sense amplifier;

selectively accessing at least one of a plurality of memory cells with an n-channel field effect transistor;

applying a voltage to a read word line to provide a body bias to the n-channel field effect transistor; and

charging a trench plate trench capacitor of one of the plurality of memory cells using the n-channel field effect transistor.

2. The method of claim 1, wherein selectively accessing at least one of a plurality of memory cells comprises raising a gate voltage of the n-channel field effect transistor to a first selected voltage.

3. The method of claim 2, wherein raising the gate voltage of the n-channel field effect transistor comprises raising the gate voltage of the n-channel field effect transistor to approximately three volts.

4. The method of claim 1, wherein applying a voltage to a read word line comprises applying a voltage to a read word line to raise a threshold voltage of the n-channel field effect transistor to about one volt.

5. The method of claim 1, wherein applying a voltage to a read word line comprises applying a voltage of approximately 0.7 volts to the read word line.

6. A method of storing data in a memory device, the method comprising:

detecting current signals from an input device using a current sense amplifier;

selectively accessing at least one of a plurality of memory cells with an n-channel field effect transistor;

charging a trench plate trench capacitor of one of the plurality of memory cells using the n-channel field effect transistor; and

coupling a base of a bipolar junction transistor in parallel with the n-channel field effect transistor at a first selected voltage.

7. The method of claim 6, wherein coupling the base of a bipolar junction transistor comprises coupling the base of a bipolar junction transistor at approximately 0.7 volts.

8. A method of storing data in a memory device, the method comprising:

detecting current signals from an input device using a current sense amplifier;

selectively accessing at least one of a plurality of memory cells with an n-channel field effect transistor;

charging a trench plate trench capacitor of one of the plurality of memory cells using the n-channel field effect transistor; and

applying a first voltage to a read word line coupled to a base of a bipolar junction transistor in parallel with the n-channel field effect transistor.

9. The method of claim 8, wherein applying a first voltage to a read word line comprises applying a voltage to a read word line to raise a threshold voltage of the n-channel field effect transistor to about one volt.

10. The method of claim 8, wherein applying a first voltage to a read word line comprises applying a voltage of approximately 0.7 volts to the read word line.

11. A method of storing data in a memory device, the method comprising:

detecting current signals from an input device using a current sense amplifier;

selectively accessing at least one of a plurality of memory cells with an n-channel field effect transistor by activating a write word line;

charging a trench plate trench capacitor of one of the plurality of memory cells using the n-channel field effect transistor; and

applying a voltage to a read word line coupled to a base of a bipolar junction transistor in parallel with the n-channel field effect transistor.

12. The method of claim 11, wherein applying a voltage to a read word line comprises applying a voltage to a read word line to raise a threshold voltage of the n-channel field effect transistor to about one volt.

13. The method of claim 11, wherein applying a voltage to a read word line comprises applying a voltage of approximately 0.7 volts to the read word line.

14. The method of claim 11, wherein selectively accessing at least one of a plurality of memory cells comprises raising a voltage of the wire word line to the first selected voltage.

15. The method of claim 14, wherein raising the gate voltage of the n-channel field effect transistor comprises raising the gate voltage of the n-channel field effect transistor to approximately three volts.

16. A method of storing data in a memory device, the method comprising:

detecting current signals from an input device using a current sense amplifier;

selectively accessing at least one of a plurality of memory cells with an n-channel field effect transistor;

charging a trench plate trench capacitor of one of the plurality of memory cells using the n-channel field effect transistor;

coupling a base of a bipolar junction transistor in parallel with the n-channel field effect transistor at a first selected voltage; and

operating the n-channel field effect transistor and the bipolar junction transistor using one volt power supply voltages.

17. The method of claim 16, wherein the first selected voltage comprises a voltage to raise a threshold voltage of the n-channel field effect transistor to about one volt.

18. The method of claim 16, wherein the first selected voltage comprises a voltage of approximately 0.7 volts.

19. A method of storing data in a memory device, the method comprising:

detecting current signals from an input device using a current sense amplifier; selectively accessing at least one of a plurality of memory cells with an n-channel field effect transistor;

charging a trench plate trench capacitor of one of the plurality of memory cells using the n-channel field effect transistor;

applying a first voltage to a read word line coupled to a base of a bipolar junction transistor in parallel with the n-channel field effect transistor; and

operating the n-channel field effect transistor and the bipolar junction transistor using one volt power supply voltages.

20. The method of claim 19, wherein applying a first voltage to a read word line comprises applying a voltage to a read word line to raise a threshold voltage of the n-channel field effect transistor to about one volt.

21. The method of claim 19, wherein applying a first voltage to a read word line comprises applying a voltage of approximately 0.7 volts to the read word line.

22. A method of storing data in a memory device, the method comprising:

detecting current signals from an input device using a current sense amplifier;

selectively accessing at least one of a plurality of memory cells with an n-channel field effect transistor by activating a write word line;

applying a voltage to a read word line to provide a body bias to the n-channel field effect transistor;

charging a trench plate trench capacitor of one of the plurality of memory cells using the n-channel field effect transistor; and

coupling a base of a bipolar junction transistor in parallel with the n-channel field effect transistor at a first selected voltage.

23. The method of claim 22, wherein the first selected voltage comprises a voltage to raise a threshold voltage of the n-channel field effect transistor to about one volt.

24. The method of claim 22, wherein the first selected voltage comprises a voltage of approximately 0.7 volts.
Description



TECHNICAL FIELD OF THE INVENTION

The present invention relates generally to integrated circuits and in particular the present invention relates to integrated circuit memory devices.

BACKGROUND OF THE INVENTION

Complimentary metal oxide semiconductor field effect transistors (CMOS FETs) are prevalent in integrated circuit technology because they generally demand less power than bipolar transistors. Threshold voltage variations of CMOS transistors, however, are beginning to pose impractical limitations on CMOS devices as power supply voltages are reduced. In a 0.2 micron CMOS technology a 0.4 V distribution in threshold voltages might be anticipated. With a one volt power supply, this distribution can cause large variations in the speed of a logic circuit, such as those used in integrated memory circuits. For example, a threshold voltage of 0.6 V is required in a DRAM memory cell access transistor to insure low sub-threshold voltage leakage currents. If a threshold voltage distribution of 0.4 volts is experienced, there will be instances where little or no excess voltage above threshold voltage is available. As such, data transfer from a memory cell via such a transistor will be very slow.

A basic problem with CMOS access transistors results from the fact that CMOS devices do not function well at low voltages and require the use of higher than desirable power supply voltages, currently around two volts in 0.2 micron CMOS technology. Various techniques have been proposed to compensate for this in CMOS technology. For example, some form of transistor forward body bias, or specialized circuits to compensate for threshold voltage variations can be used.

Various types of lateral MOS transistors have been described and utilized in CMOS technology. Lateral bipolar transistors have received renewed interest with the advent of bipolar complementary metal oxide semiconductor (BiCMOS) technologies.

For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an access device for use in a low voltage memory device which performs fast read access of memory data.

SUMMARY OF THE INVENTION

The above mentioned problems with integrated circuit memory devices and other problems are addressed by the present invention and which will be understood by reading and studying the following specification. A memory cell access device is described which uses a combination of bipolar junction and CMOS transistors as access devices to store and read data on a trench plate trench capacitor.

In particular, one embodiment of the present invention provides a memory cell access device that has two access transistors. The first access transistor is an n-channel field effect transistor (FET) that is coupled between a trench plate trench capacitor and a data communication line. The second access transistor is an NPN bipolar junction transistor that is coupled between the trench plate trench capacitor and the data communication line. The n-channel access transistor and the NPN bipolar junction transistor are connected in parallel, and a base connection of the NPN bipolar junction transistor is coupled to a body of the n-channel field effect transistor.

In another embodiment, a low voltage memory cell access device fabricated as a vertical pillar structure is provided. The memory cell access device includes a field effect transistor that is coupled between a trench plate trench capacitor and a data communication line. The memory cell access device also includes a bipolar junction transistor that is coupled between the memory cell and the data communication line. The field effect transistor and the bipolar junction transistor are connected in parallel, with a base connection of the bipolar junction transistor that is coupled to a body of the field effect transistor.

In another embodiment, a memory device having a low voltage supply is provided. The memory device comprises a plurality of memory cells, a plurality of data communication bit lines, and a plurality of memory cell access devices coupled between the plurality of memory cells and the plurality of data communication bit lines. Each of the plurality of memory cell access devices comprises a field effect transistor and a bipolar junction transistor. The field effect transistor and the bipolar junction transistor are connected in parallel between a trench plate trench capacitor and a data communication bit line.

In another embodiment, a method of accessing a memory cell is provided. The method includes activating a field effect transistor coupled between a trench plate trench capacitor and a data communication line for writing data to the memory cell, and activating a bipolar junction transistor coupled between the trench plate trench capacitor and a data communication line for reading a charge stored on the memory cell.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an embodiment of a memory device according to the teachings of the present invention.

FIG. 2 is an embodiment of a portion of an array of memory cells according to the teachings of the present invention.

FIG. 3A is a schematic diagram that illustrates an embodiment of a memory cell with a vertical access device according to the teachings of the present invention.

FIG. 3B is a cross sectional view that illustrates an integrated circuit embodiment of the vertical access device of FIG. 3A.

FIG. 3C is a cross sectional view that illustrates another integrated circuit embodiment of the vertical access device of FIG. 3A.

DETAILED DESCRIPTION

In the following detailed description of the invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The terms wafer and substrate used in the following description include any structure having an exposed surface with which to form the integrated circuit (IC) structure of the invention. The term substrate is understood to include semiconductor wafers. The term substrate is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. Both wafer and substrate include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art. The term conductor is understood to include semiconductors, and the term insulator is defined to include any material that is less electrically conductive than the materials referred to as conductors. The following detailed description is, therefore, not to be taken in a limiting sense.

The term "horizontal" as used in this application is defined as a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term "vertical" refers to a direction perpendicular to the horizonal as defined above. Prepositions, such as "on", "side" (as in "sidewall"), "higher", "lower", "over" and "under" are defined with respect to the conventional plane or surface being on the top surface of the wafer or substrate, regardless of the orientation of the wafer or substrate.

Smaller integrated circuit devices combined with the development of vertical integrated circuit structures, make it possible to use bipolar junction transistor action rather than just field effect transistor operation. In fact, a bipolar junction transistor structure can be used as a data read access device and a field effect transistor used as a data write access device, as described herein. Below, an embodiment of the present invention is described in terms of a dynamic random access memory (DRAM) device. Embodiments of an access device constructed according to the teachings of the present invention are also shown and described. It is understood, however, that these embodiments are provided by way of example and not by way of limitation.

Dram Device

FIG. 1 is a simplified block diagram of an embodiment of a memory device incorporating access devices constructed according to the teachings of the present invention. Memory device 100 includes an array of memory cells 102, address decoder 104, row access circuitry 106, column access circuitry 108, control circuitry 110, and Input/Output circuit (I/O) 112.

In one embodiment, each cell in array 102 includes an access device with a bipolar junction transistor coupled in parallel with a field effect transistor between a data communication or digit line and a trench plate trench capacitor. The access device is used to charge and discharge the trench plate trench capacitor to store and read data from the memory cell. The field effect transistor charges the capacitor. The bipolar junction transistor reads the charge stored on the capacitor by discharging the capacitor and providing the current to a current sense amplifier. The bipolar junction transistor typically conducts a higher current compared to its counterpart field effect transistor. Thus, the access device provides the advantage of increased speed in reading the data stored in the memory cell by allowing the capacitor to be discharged more quickly.

Memory device 100 can be coupled to an external microprocessor 114, or memory controller for memory accessing. Memory device 100 receives control signals from the microprocessor 114, such as WE*, RAS* and CAS* signals. Memory device 100 is used to store data which is accessed via I/O lines. It will be appreciated by those skilled in the art that additional circuitry and control signals can be provided, and that the memory device of FIG. 1 has been simplified to help focus on embodiments of the present invention.

It will be understood that the above description of a DRAM is intended to provide a general understanding of the memory and is not a complete description of all the elements and features of a DRAM. Further, the embodiments of the present invention are equally applicable to any size and type of memory circuit and are not intended to be limited to the DRAM described above. Other alternative types of devices include SRAM or Flash memories. Additionally, the DRAM could be a synchronous DRAM commonly referred to as SGRAM, SDRAM, SDRAM II, and DDR SDRAM, as well as Synchlink or Rambus DRAMs.

Referring to FIG. 2, an embodiment of a portion of array 102 is provided. The simplified schematic diagram illustrates a portion of a column of the array 102. The column is generally defined by a pair of data communication or digit lines 120 and 122. Access devices 124 are located along the digit lines for coupling trench plate trench capacitors 126 to a digit line. Access devices 124 include field effect transistor 123 in parallel with bipolar junction transistor 125. The field effect transistors 123 are activated by a word line (W-WL) to write data to a trench plate trench capacitor, which defines a row of the memory array. The bipolar junction transistors 125 are activated by a word line (R-WL) to read data from a trench plate trench capacitor.

Current sense amplifier 128 is provided to detect current signals provided to the digit lines by a bipolar junction transistor during a read operation. In one embodiment, a clamped bit line sense amplifier, as shown, can be used. The current from the digit lines are injected to the cross coupled pair of inverters (M1/M3 and M2/M4). Transistors M5 and M6 serve to clamp the digit lines at a fixed voltage, e.g., 0.7 volts. The impedance looking into the source of transistors M1 and M2 is very low but the current injected here from the data lines serves to upset the cross coupled inverters which provides a high speed large signal output. Alternatively, other sense amplifiers can be used that allow a current from a trench plate trench capacitor to be sensed.

As described above, a large variation in a threshold voltage of the field effect access transistors can result in slow data access. This slow access is most troubling in data read operations. Embodiments of the present invention avoid this access speed problem while maintaining a higher threshold voltage. That is, for access devices 124 in a DRAM circuit a larger threshold voltage value is desired to reduce memory cell leakage and increase retention time in the memory cells. By using the bipolar junction transistor in parallel with the field effect transistor, a larger threshold voltage can be maintained without increasing cell leakage and reducing retention time.

Memory Cell Access Device

FIG. 3A illustrates a schematic diagram of a vertical access device 200 having both a bipolar junction transistor 202 and a metal-oxide semiconductor field effect transistor (MOSFET) 204 which can be formed in either bulk or SOI technology. Bipolar junction transistor 202 is an NPN transistor having emitter 206, collector 208 and base 210. Transistor 204 is an n-channel MOSFET having first source/drain region 212, second source/drain region 214 and gate 216. The access device can be fabricated as a single unit, or as separate transistors.

FIGS. 3B and 3C provide alternative fabricated integrated circuit embodiments of an access device 300 constructed according to the teachings of the present invention. FIG. 3B is a bulk silicon embodiment of an access device formed in a single pillar of monocrystalline semiconductor material. Access device 300 includes a parallel combination of a bipolar junction transistor and a field effect transistor. Access device 300 is coupled to trench plate trench capacitor 301. Access device 300 includes n+ semiconductor layer 304. Layer 304 serves as an emitter for the bipolar junction transistor, a source/drain region for the field effect transistor and a plate of the trench plate trench capacitor. P-doped semiconductor layer 306 is fabricated on layer 304. The vertical doping profile of region 306 is varied, as explained below, to optimize bipolar transistor action. An n+ semiconductor layer 312 is provided on top of layer 306. Polysilicon region 316 is fabricated to operate as a gate isolated from layer 306 by gate oxide layer 314. A polysilicon base contact 320 is provided opposite gate 316 on oxide layer 319 and in contact with region 306. Further, trench plate trench capacitor 301 includes a polysilicon mesh (POLY) that surrounds a portion of layer 304. The polysilicon mesh forms a second plate of capacitor 301.

FIG. 3C is an SOI embodiment of an access device 300 constructed according to the teachings of the present invention. In this embodiment, access device 300 includes n+ semiconductor layer 304 that extends down through a polysilicon mesh (POLY). The polysilicon mesh and layer 304 are formed on insulator layer 303, e.g., an oxide, or insulating base layer. The remaining components of the access device are substantially the same as the access device of FIG. 3B, although fabrication techniques may differ.

A vertical doping profile of region 306 of the access device is optimized for both bipolar transistor action and biasing the body of the field effect transistor to a value around 0.9 V to forward bias the base emitter junction. The doping profile is controlled so that the top portion 310 of layer 306 is more heavily doped p-type than a bottom region 308. This difference in doping is represented by the designations P and P-. The actual doping levels with respect to other structures or base layers can be varied, and relative doping levels between the top and bottom regions of layer 306 is only represented herein.

One way to create the difference in the doping profile is to use the effects of the fabrication of emitter 312. When the emitter, or top n-type layer 312, is fabricated a relatively higher base doping level near emitter 312 can be created. This doping profile is required in a vertical NPN transistor to give field-aided diffusion in the base and a high current gain, .beta.. If the base doping is around 10.sup.18 /cm.sup.3, as is common in NPN transistors, then region 310 also serves to make the n-channel vertical MOSFET enhancement mode, which is difficult to achieve by other techniques since implantations for threshold voltage adjustment cannot be conveniently done.

The following comparison further illustrates the advantage of using a bipolar junction transistor for data read operations in a low voltage memory. If n-channel field effect transistor 204 of FIG. 3A is used to discharge the capacitor, it is customary to precharge a data communication "bit" line to 1/2+L V.sub.DD, or in this illustration 1.5 volts. The peak transfer current I.sub.D is estimated to be around 40 .mu.A assuming a Vt of 0.5 volts. That is, the drain current is calculated by: ##EQU1##

If the memory cell is assumed to store 50 fC, the charge from the memory cell requires 1.2 nano-seconds to transfer to the bit line through transistor 204.

A faster data transfer is possible if bipolar access transistor 202 is used with a clamped bit line where the bit line is precharged to a lower voltage, such as 0.7 V. The peak bipolar current is determined mostly by the base current I.sub.B and the variation of current gain, .beta., with peak current. Assuming a base current of 4.0 .mu.A, a peak collector value of 400 .mu.A is estimated by:

I.sub.C =.beta.I.sub.B where .beta.=100

If the memory cell is assumed to store the 70 fC, the charge from the memory cell requires only 0.18 nano-seconds to transfer to the bit line. A substantial decrease in transfer time, therefore, is experienced by using a bipolar access transistor during read operations in the low voltage memory.

Access Operations in a DRAM Embodiment

During a write operation the base of BJT transistor 202 is coupled to a low voltage, such as 0.7 volts. The body potential in layer 306, therefore, is held at the low level resulting in a MOSFET body bias which increases as the memory is charged due to an elevated bit line potential. As a result, the threshold voltage of transistor 204 rises to around one volt. A bootstrapped voltage as known to those skilled in the art can be used to drive the gate voltage above three volts, such as four volts. This booted voltage is necessary because the supply voltage is limited to three volts, and a second supply is typically not provided. The time required for the write operation is not critical and can be much longer than the read response. Thus, the reduced power requirements of the MOSFET are desirable.

During a read operation the bit lines are clamped to a low voltage (near the base low voltage), in this example 0.7 V. The voltage of the bit lines does not change significantly during a read operation, unlike in a memory using a conventional voltage sense amplifier, since here current not voltage is being sensed. During a read operation, the read word line goes to a higher voltage, such as 1.4 V, to forward bias the base-emitter junction and turn on the bipolar transistor 202. The bipolar transistor will be strongly forward biased and quickly discharge the charge stored on the memory storage capacitor onto the bit line where it can be sensed as a current. The memory cell discharges to about 0.7 V at which point the bipolar transistor saturates and stops functioning. The memory cell data state voltage levels are therefore approximately two volts when charged, and 0.7 V when discharged.

It is estimated that a bit line current sense amplifier is about eight times faster than the a bit line differential voltage sense amplifier commonly used in DRAMs. Further, as detailed above, current transfer from a memory cell to a bit line using the bipolar transfer device is about eight times faster than an n-channel MOSFET transfer device. The net result is that the present invention, when used in a low voltage memory device for data read operations, is about eight times faster than commonly used CMOS DRAMs. Further, a vertical access transistor device with a trench plate trench capacitor is only 4 F.sup.2 in area. A DRAM according to the present invention, therefore, is about one-half the area of conventional DRAM's and about eight times faster.

In operation, the bipolar device would be used for reads and the MOSFET device on the other side of the device pillar can most conveniently be used for write operations to store information on the memory capacitor in a conventional manner. The present invention can be scaled to lower power supply voltages and smaller dimensions, in which case the use of the bipolar access device becomes yet more advantageous. For one volt power supply voltages, the threshold voltage variations of MOSFETs will become a large fraction of the total voltage available.

Conclusion

Embodiments of an access device for a memory device have been described which use an n-channel field effect transistor and a bipolar junction transistor coupled in parallel between a trench plate trench capacitor and a data communication line. A base connection of the NPN bipolar junction transistor has been described as coupled to a body of the n-channel access transistor to control threshold voltage variations of the n-channel field effect transistor. During operation the n-channel field effect transistor is used for writing data to a trench plate trench capacitor, while the NPN bipolar junction transistor is used for read operations in conjunction with a current sense amplifier circuit. The access transistors are described as fabricated as a single vertical pillar.

Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention.

* * * * *

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