Structures and method for an open bit line DRAM device are provided. The
open bit line DRAM device includes an array of memory cells. Each memory
cell in the array of memory cells includes a pillar extending outwardly
from a semiconductor substrate. The pillar includes a single crystalline
first contact layer and a single crystalline second contact layer
separated by an oxide layer. In each memory cell a single crystalline
vertical transistor is formed along side of the pillar. The single
crystalline vertical transistor includes an ultra thin single crystalline
vertical first source/drain region coupled to the first contact layer, an
ultra thin single crystalline vertical second source/drain region coupled
to the second contact layer, an ultra thin single crystalline vertical
body region which opposes the oxide layer and couples the first and the
second source/drain regions, and a gate opposing the vertical body region
and separated therefrom by a gate oxide. A plurality of buried bit lines
are formed of single crystalline semiconductor material and disposed below
the pillars in the array memory cells for interconnecting with the first
contact layer of column adjacent pillars in the array of memory cells.
Also, a plurality of word lines are included. Each word line is disposed
orthogonally to the plurality of buried bit lines in a trench between rows
of the pillars for addressing gates of the single crystalline vertical
transistors that are adjacent to the trench.
Other References
Hergenrother, J.M., "The Vertical Replacement-Gate (VRG) MOSFET: A 50nm
Vertical MOSFET with Lithography-Independent Gate Length", IEEE, pp.
75-78, (1999).
Kalavade, P., et al., "A Novel sub-10nm Transistor", IEEE Device Research
Conference, Denver, Co., pp. 71-72, (2000).
Xuan, P., et al., "60nm Planarized Ultra-thin Body Solid Phase Epitaxy
MOSFETs", IEEE Device Research Conference, Denver, CO, pp. 67-68, (2000).
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