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United States Patent |
6,539,490
|
Forbes
,   et al.
|
March 25, 2003
|
Clock distribution without clock delay or skew
Abstract
The present invention provides a method and apparatus, for integrated
circuits, that is able to generate clock signals at different destination
points with little or no clock signal delay or skew. A slow rising input
clock signal is propagated across a low loss transmission line. The slow
rising input signal creates a region of substantially no clock signal
delay between the signal at the beginning of the low loss transmission
line and the signal at the end of the low loss transmission line.
Comparators are used to compare the signals at the beginning and end of
the low loss transmission lines and compare them to a reference signal.
The compared signals are sampled during the region of substantially no
clock signal delay or skew. The sampled clock signals with substantially
no delay are sent to local destination points or other low loss
transmission lines within the integrated circuit to transmit the signal to
remote destination points.
Inventors:
|
Forbes; Leonard (Corvallis, OR);
Ahn; Kie Y. (Chappaqua, NY)
|
Assignee:
|
Micron Technology, Inc. (Boise, ID)
|
Appl. No.:
|
385379 |
Filed:
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August 30, 1999 |
Current U.S. Class: |
713/401; 713/503; 327/141 |
Intern'l Class: |
G06F 001/12 |
Field of Search: |
713/400,401,500,503
327/141
|
References Cited [Referenced By]
U.S. Patent Documents
Other References
Edelstein et al; "Full Copper Wiring in a Sub-0.25 .mu.m CMOS ULSI
Technology"; Tech. Digest of 1997 IEDM; pp. 773-776.
Venkatesan et al.; "A High Performance 1.8V, 0.20 .mu.m CMOS Technology
with Copper Metallization"; Tech. Digest of 1997 IEDM; pp. 769-772.
Matsuura et al.; "A Highly Reliable Self-planarizing Low-k Internal
Dielectric for Sub-quarter Micron Interconnects"; Tech. Digest of 1997
IEDM; pp. 785-788.
Aoki et al.; "A Degradation-Free Cu/HSQ Damascene Technology using Metal
Mask Patterning and Post-CMP Cleaning by Electrolytic Ionized Water";
Tech. Digest of 1997 IEDM; pp. 777-781.
Rabaey; "Digital integrated Circuits", A Design Perspective, Prentice Hall
Electronics and VSLI Series 1996; pp. 482-493.
|
Primary Examiner: Lee; Thomas
Assistant Examiner: Du; Thuan
Attorney, Agent or Firm: Dickstein, Shapiro, Morin & Oshinsky LLP
Claims
What is claimed as new and desired to be protected by Letters Patent of the
United States is:
1. A circuit for reducing signal skew among a plurality of output signals
comprising:
a source of clock signals;
a first low loss transmission line coupled to an output of said clock
signal source; and
a first output terminal at a first end of said transmission line and a
second output terminal at a second end of said transmission line;
said clock input signal source generating a clock signal having a rise rate
such that signals appearing at said first and second output terminals have
substantially no signal skew.
2. The circuit of claim 1 further comprising a first comparator having one
input connected to a reference voltage and another input connected to said
first output terminal and a second comparator having one input connected
to said reference voltage and another input connected to said second
output terminal; and
the signals provided at the respective outputs of said first and second
comparators having substantially no signal skew.
3. The circuit of claim 2, wherein said reference voltage is equal to half
the voltage value of said generated clock signal.
4. The circuit of claim 1, wherein said rate is slower than twice the time
it takes for said clock signal to travel down said transmission line.
5. The circuit of claim 1, wherein said transmission line has an impedance
greater than 50 ohms.
6. The circuit of claim 1, wherein said first transmission line is a low
loss transmission line.
7. The circuit of claim 6, wherein said low loss transmission line has a
resistance much less than the square root of four times the inductance
divided by the capacitance of the line.
8. The circuit of claim 7, wherein said low loss transmission line
comprises a conductor embedded in a trench of an integrated circuit.
9. The circuit of claim 8, wherein said conductor comprises a
low-resistivity metal.
10. The circuit of claim 8, wherein said trench includes an insulator
surrounding said conductor.
11. The circuit of claim 10, wherein said insulator comprises a low-k
dielectric constant material.
12. The circuit of claim 8, wherein said trench includes posts for
supporting said transmission line.
13. The circuit of claim 2, further comprising:
a second low loss transmission line connected to an output of at least one
of said first and second comparators; and
a first output terminal at a first end of said second transmission line and
a second output terminal at a second end of said second transmission line;
said output of said one comparator having a rise rate such that signals
appearing at said first and second output terminal of said second
transmission line have substantially no skew.
14. The circuit of claim 13, further comprising a third comparator having
one input connected to a reference voltage and another input connected to
said first output terminal of said second transmission line and a fourth
comparator having one input connected to said reference voltage and
another input connected to said second output terminal of said second
transmission line; and
the signals provided at the respective outputs of said third and fourth
comparators having substantially no skew.
15. The circuit of claim 14, further comprising a delay circuit;
said signals at the outputs of said first and second comparators passing
through said delay circuit such that they have substantially no skew with
the signals at the output of said third and fourth comparators.
16. A circuit for reducing signal skew among a plurality of output signals
comprising:
a source for generating a plurality of clock signals in phase;
a plurality of first low loss transmission lines coupled to receive a
respective one of said clock signals; and
a first output terminal at a first end of each one of said first
transmission lines and a second output terminal at a second end of each
one of said first transmission lines;
said source generating said in phase clock signals each with a rise rate
such that signals appearing at said first and second output terminals of
each of said first transmission lines have substantially no signal skew.
17. The circuit of claim 16, further comprising:
a plurality of first comparators, wherein each one of said first
comparators has one input connected to a reference voltage and another
input connected to a first output terminal of a respective first
transmission line; and
a plurality of second comparators, wherein each of said second comparators
has one input connected to said reference voltage and another input
connected to a second output terminal of a respective first transmission
line; and
the signals provided at the respective outputs of said first and second
comparators having substantially no skew.
18. The circuit of claim 17, wherein said reference voltage is equal to
half the voltage value of said generated clock signal.
19. The circuit of claim 16, wherein said rate is slower than twice the
time it takes for said clock signal to travel down one of said
transmission lines.
20. The circuit of claim 16, wherein each one of said transmission lines
has an impedance greater than 50 ohms.
21. The circuit of claim 16, wherein each one of said first transmission
lines is a low loss transmission line.
22. The circuit of claim 21, wherein each one of said low loss transmission
lines has a resistance much less than the square root of four times the
inductance divided by the capacitance of the line.
23. The circuit of claim 21, wherein each one of said low loss transmission
lines comprises a conductor embedded in a trench of an integrated circuit.
24. The circuit of claim 23, wherein said conductor comprises a
low-resistivity metal.
25. The circuit of claim 23, wherein said trench includes an insulator
surrounding said conductor.
26. The circuit of claim 25, wherein said insulator comprises a low-k
dielectric constant material.
27. The circuit of claim 23, wherein said trench includes posts for
supporting said transmission line.
28. The circuit of claim 17, further comprising:
a plurality of second low loss transmission lines coupled to receive a
respective one of said clock signals from said first or second
comparators; and
a first output terminal at a first end of each one of said second
transmission lines and a second output terminal at a second end of each
one of said second transmission lines;
said signals from said comparators having said in phase clock signals each
with a rise rate such that signals appearing at said first and second
output terminals of each of said second transmission lines have
substantially no skew.
29. The circuit of claim 28, further comprising:
a plurality of third comparators, wherein each one of said third
comparators has one input connected to a reference voltage and another
input connected to a respective said first output terminal of said second
transmission lines; and
a plurality of fourth comparator, wherein each one of said fourth
comparators has one input connected to said reference voltage and another
input connected to a respective said second output terminal of said second
transmission lines; and
the signals provided at the respective outputs of said third and fourth
comparators having substantially no skew.
30. The circuit of claim 29, further comprising:
a plurality of delay circuits, wherein at least one of the signals at the
outputs of said plurality of first and second comparators passes through
one of said plurality of delay circuits such that the signal has
substantially no skew with the signals at the outputs of said plurality of
said third and fourth comparators.
31. A processor system comprising:
a processor;
a circuit connected to said processor for reducing signal skew among a
plurality of output signals comprising:
a source of clock signals;
a first low loss transmission line coupled to an output of said clock
signal source; and
a first output terminal at a first end of said transmission line and a
second output terminal at a second end of said transmission line;
said clock input signal source generating a clock signal having a rise rate
such that signals appearing at said first and second output terminals have
substantially no signal skew.
32. The processor system of claim 31, further comprising a first comparator
having one input connected to a reference voltage and another input
connected to said first output terminal and a second comparator having one
input connected to said reference voltage and another input connected to
said second output terminal; and
the signals provided at the respective outputs of said comparators having
substantially no signal skew.
33. The processor system of claim 32, wherein said reference voltage is
equal to half the voltage value of said generated clock signal.
34. The processor system of claim 31, wherein said rate is slower than
twice the time it takes for said clock signal to travel down said
transmission line.
35. The processor system of claim 31, wherein said transmission line has an
impedance greater than 50 ohms.
36. The processor system of claim 31 wherein said first transmission line
is a low loss transmission line.
37. The processor system of claim 36, wherein said low loss transmission
line has a resistance much less than the square root of four times the
inductance divided by the capacitance of the line.
38. The processor system of claim 36, wherein said low loss transmission
line comprises a conductor embedded in a trench of an integrated circuit.
39. The processor system of claim 38, wherein said conductor comprises a
low-resistivity metal.
40. The processor system of claim 38, wherein said trench includes an
insulator surrounding said conductor.
41. The processor system of claim 40, wherein said insulator comprises a
low-k dielectric constant material.
42. The processor system of claim 38, wherein said trench includes posts
for supporting said transmission line.
43. The processor system of claim 32, further comprising:
a second low loss transmission line connected to an output of at least one
of said first and second comparators; and
a first output terminal at a first end of said second transmission line and
a second output terminal at a second end of said second transmission line;
said output of said one comparator having a rise rate such that signals
appearing at said first and second ends of said second transmission line
have substantially no skew.
44. The processor system of claim 43, further comprising a third comparator
having one input connected to a reference voltage and another input
connected to said first output terminal of said second transmission line
and a fourth comparator having one input connected to said reference
voltage and another input connected to said second output terminal of said
second transmission line; and
the signals provided at the respective outputs of said third and fourth
comparators having substantially no skew.
45. The processor system of claim 44, further comprising a delay circuit;
said signals at the outputs of said first and second comparators passing
through said delay circuit such that they have substantially no skew with
the signals at the output of said third and fourth comparators.
46. A processor system comprising:
a processor;
a circuit connected to said processor for reducing signal skew among a
plurality of output signals comprising:
a source for generating a plurality of clock signals in phase;
a plurality of first low loss transmission lines coupled to receive a
respective one of said clock signals; and
a first output terminal at a first end of each one of said first
transmission lines and a second output terminal at a second end of each
one of said first transmission lines;
said source generating said in phase clock signals each with a rise rate
such that signals appearing at said first and second output terminals of
each of said first transmission lines have substantially no signal skew.
47. The processor of claim 46, further comprising:
a plurality of first comparators, wherein each one of said first
comparators has one input connected to a reference voltage and another
input connected to a first output terminal of a respective first
transmission line; and
a plurality of second comparators, wherein each of said second comparators
has one input connected to said reference voltage and another input
connected to a second output terminal of a respective first transmission
line; and
the signals provided at the respective outputs of said first and second
comparators having substantially no skew.
48. The processor of claim 47, wherein said reference voltage is equal to
half the voltage value of said generated clock signal.
49. The processor of claim 46, wherein said rate is slower than twice the
time it takes for said clock signal to travel down one of said
transmission lines.
50. The processor of claim 46, wherein each one of said transmission lines
has an impedance greater than 50 ohms.
51. The processor of claim 46, wherein each one of said first transmission
lines is a low loss transmission line.
52. The processor of claim 51, wherein each one of said low loss
transmission lines has a resistance much less than the square root of four
times the inductance divided by the capacitance of the line.
53. The processor of claim 51, wherein each one of said low loss
transmission lines comprises a conductor embedded in a trench of an
integrated circuit.
54. The processor of claim 53, wherein said conductor comprises a
low-resistivity metal.
55. The processor of claim 53, wherein said trench includes an insulator
surrounding said conductor.
56. The processor of claim 55, wherein said insulator comprises a low-k
dielectric constant material.
57. The processor of claim 53, wherein said trench includes posts for
supporting said transmission line.
58. The processor of claim 47, further comprising:
a plurality of second low loss transmission lines coupled to receive a
respective one of said clock signals from said first or second
comparators; and
a first output terminal at a first end of each one of said second
transmission lines and a second output terminal at a second end of each
one of said second transmission lines;
said signals from said comparators generating said in phase clock signals
each with a rise rate such that signals appearing at said first and second
output terminals of each of said second transmission lines have
substantially no skew.
59. The processor of claim 58, further comprising:
a plurality of third comparators, wherein each one of said third
comparators has one input connected to a reference voltage and another
input connected to a respective said first output terminal of said second
transmission lines; and
a plurality of fourth comparators, wherein each one of said fourth
comparators has one input connected to said reference voltage and another
input connected to a respective said second output terminal of said second
transmission lines; and
the signals provided at the respective outputs of said third and fourth
comparators having substantially no skew.
60. The processor of claim 59, further comprising:
a plurality of delay circuits, wherein at least one of the signals at the
outputs of said plurality of first and second comparators passes through
one of said plurality of delay circuits such that the signal has
substantially no skew with the signals at the outputs of said plurality of
said third and fourth comparators.
61. A method for reducing clock signal skew among a plurality of signals
comprising the steps of:
generating at least one clock signal and transmitting said signal through
at least one first low loss transmission line having a first output
terminal at a first end of said first transmission line and a second
output terminal at a second end of said first transmission line;
said clock signal having a rise rate such that signals appearing at said
first and second ends of said first transmission lines have substantially
no skew.
62. The method of claim 61, further including the step of comparing each of
the signals at said first and second ends of said first transmission line
with a reference voltage, and providing output signals having
substantially no skew when said comparison show that said signals at each
of said first and second ends are larger than said reference voltage.
63. The method of claim 62, further including the steps of:
transmitting at least one of said output signals having substantially no
skew through at least one second low loss transmission line;
wherein said second low loss transmission line has a first output terminal
at a first end and a second output terminal at a second end of said second
low loss transmission line; and
said output signal having a rise rate such that signals appearing at said
first and second ends of said second transmission line have substantially
no skew.
64. The method of claim 63, further including the step of comparing each of
the signals at said first and second ends of said second transmission line
with a reference voltage, and providing output signals having
substantially no skew when said comparison show that said signals at each
of said first and second ends of said second transmission line are larger
than said reference voltage.
65. The method of claim 64, further including the step of delaying the
signals at the first and second ends of the first low loss transmission
line so that there is substantially no skew between the signals of the
first and seconds ends of both the first and the second low loss
transmission lines.
66. A circuit for reducing signal skew among a plurality of output signals
comprising:
a source for generating a plurality of clock signals in phase;
at least one first low loss transmission line coupled to an output of said
source;
said first low loss transmission line having a first output terminal at a
first end of said transmission line and a second output terminal at a
second end of said transmission line;
a first comparators having one input connected to a reference voltage and
another input connected to said first output terminal and a second
comparator having one input connected to a reference voltage and another
input connected to said second output terminal;
said first and second comparators have an output line;
wherein said signal source generates a clock signal having a rise rate such
that signals appearing at said first and second output terminals have
substantially no skew; and
wherein said low loss transmission line comprises a conductor embedded in a
trench of an integrated circuit, wherein said low loss transmission line
has an impedance greater than 50 ohms and a resistance much greater then
the square root of four times the inductance divided by the capacitance of
the line.
67. The circuit of claim 66, wherein said conductor comprises a
low-resistivity metal.
68. The circuit of claim 66, wherein said trench includes an insulator
surrounding said conductor.
69. The circuit of claim 66, wherein said insulator comprises a low-k
dielectric constant material.
70. The circuit of claim 66, wherein said trench includes posts for
supporting said transmission line.
71. The circuit of claim 66, further comprising:
a plurality of second low loss transmission lines coupled to the output of
said first and second comparators; and
a first output terminal at a first end of each one of said second
transmission lines and a second output terminal at a second end of each
one of said second transmission lines;
said signals from said comparators having said in phase clock signals each
with a rise rate such that signals appearing at said first and second
output terminals of each of said second transmission lines have
substantially no skew.
72. The circuit of claim 71, further comprising:
a plurality of third comparators, wherein each of said third comparators
has one input connected to a reference voltage and another input connected
to said first output terminal of a respective second transmission line;
and
a plurality of fourth comparators, wherein each of said fourth comparators
has one input connected to said reference voltage and another input
connected to said second output terminal of a respective second
transmission line; and
the signals provided at the respective outputs of said third and fourth
comparators having substantially no skew.
73. The circuit of claim 72, further comprising a plurality of delay
circuits;
said signals at the outputs of said first and second comparators passing
through said delay circuit such that they have substantially no skew with
the signals at the output of said third and fourth comparators.
Description
FIELD OF THE INVENTION
This invention relates to integrated circuit chips, in particular, to a
method and apparatus capable of reducing clock signal skew in an
integrated circuit, between integrated circuits, and between integrated
circuits and other circuits.
BACKGROUND OF THE INVENTION
The timing of a microprocessor based circuit is controlled by one or more
clock signals. A clock signal includes periodic transitions between high
and low logic levels at high frequency. Early personal computers operated
using clock signals with a frequency near 5 MHz, but current
implementations use numerous clock sources with frequencies increasing
towards 10 GHz.
The clock signal in a computer system is used for many purposes including
to synchronize bus cycles in the system. Thus, all digital components in
the computer system initiate data operations based upon the clock signal.
Clock signals usually are generated by clock circuits and these clock
circuits can be within an integrated circuit or fabricated on a printed
circuit board. Microprocessor based circuits are often complex and include
numerous electrical components, many of which are driven by a clock
signal.
Referring to FIG. 1, a typical clock circuit 1 includes an oscillator
circuit 2, which is typically crystal controlled, which is coupled to a
clock buffer circuit 4. The oscillator circuit 2 generates a periodic
signal at a predetermined frequency. A clock buffer circuit 4 receives the
periodic signals from oscillator circuit 2 and generates multiple output
clock signals. The output clock signals are produced by output buffers
within clock buffer circuit 4. The clock signals are sent to multiple
destination points D1, D2, D3, and D4 within an integrated circuit. The
clock signals are then used to drive circuit components located at various
sites across the integrated circuit.
Although occurring extremely rapidly, electrical signals require a finite
amount of time to travel from one point to another on a circuit board. The
longer the distance through which a signal must travel, the more time it
takes for that signal to propagate the required distance. Conductive
copper, or other conductive metal pathways, commonly called traces, are
fabricated in an integrated circuit to provide conductive paths for
signals to travel from one component to another. The length of the trace
lengths between the output resistors Ro, of the clock buffer, and the
various destination points often differs. For example, if the distance
between resistor Ro and destination point D2 is shorter than the distance
between resistor Ro and D4, it will take a clock signal longer to
propagate to destination point D4 than D2. Thus, if the multiple clock
signals are in phase at resistors Ro, and each destination point has a
different associated trace length, then the clock signals arriving at the
different destination points will be out of phase. This phase difference
typically is referred to as clock skew.
Several attempts have been made to correct or reduce clock skew or delay.
One technique, attempts to modify a circuit layout by adding additional
trace length to the faster clock signal traces, to slow down the faster
clock signals, so that all of the clock signals arrive substantially in
phase at the destination points. However, this process is time consuming
and expensive because of the extensive testing, fabrication, and
subsequent modifications to form precise trace lengths to compensate for
the clock signal skew. Another way to correct or reduce clock skew is to
run the clock signals through delay circuits and adjust the delays for
respective clock signals so that all clock signals arrive at their
destination substantially in phase, which requires additional circuitry
and delay "tuning".
The problem with these attempts is that while they do mitigate clock skew
to some extent, they fail to adequately address the effects caused by the
inductance of the transmission lines. As advancing technologies increase
line lengths and device switching speeds, the inductance effects of the
transmission line starts to dominate the clock signal delay behavior.
Therefore, to adequately address the problem of clock signal skew, the
inductive transmission line effects must also be considered.
FIG. 2 illustrates a clock signal pathway which incorporates a signal
source 5, a source output impedance Zs, and a low loss transmission line
6. The low loss transmission line 6 has an overall impedance Zo shown as
line resistance R.sub.L, inductance L.sub.L, and capacitance C.sub.L. The
low loss transmission line 6 begins at node N2 and terminates at node N3.
Connected to node N3 is a termination line with a small capacitance
C.sub.S.
As seen in FIG. 2, the voltage at node N1, is simply the input voltage
which we will refer to as clock signal V1. The clock signal V1 is
generated with an input source impedance Zs and is propagated to node N2.
The signal at node N2 is divided due to the series connection of the
source impedance Zs and the line impedance Zo. The signal at node N2 is
V2. Signal V2 travels down the low loss transmission line 6 to node N3.
Since there is a termination with a small capacitance C.sub.S connected to
the low loss transmission line 6 the signal is reflected back through node
N3. The signal V3 at node N3 is therefore double the initial value of V2
because the reflected signal is added to the incoming signal. The
reflected signal is then sent back to N2 where it is also added to V2.
Ultimately, the reflected signal travels to the source impedance Zs. Since
the source impedance Zs is equal to the line impedance Zo there is no
further reflection at the N2 end.
FIG. 3, is a graphical illustration of the input signal V1, the signal V2
at node N2, and the signal V3 at node N3 for a typical fast rising clock
signal transmitted through the circuit in FIG. 2. The input clock signal
V1 rises at a fast rate, 0 volts to 5 volts in about 10 pico-seconds (ps).
The voltage V2 rises at half the rate of V1 because the V1 signal is
divided at N2, as discussed above. The signal V2 levels off at a voltage
of 2.5 Volts which is the point when V1 stops increasing, 5 Volts, this is
indicated by the point B on the V2 line. The clock signal V3, rises at
twice the rate as V2 because the reflected signal from the small
capacitance termination end is added to the incoming signal at N3. The
reflected signal is also sent back and finally reaches N2, represented as
point A on the graph which then causes the signal V2 to rise at the same
rate as V1 and V3.
As can be seen from FIG. 3, the first delay time T1, represents the time
for signal V2 to propagate down the low loss transmission line 6 from node
N2 to the node N3, where V3 starts, is about 40 ps. The second delay time
T2, represent the time for the reflected signal to travel back across the
low loss transmission line 6 from node N3 to node N2 which is also about
40 ps. Therefore, the total clock signal skew between V2 and V3 is the
time it takes for the clock signal to travel down the low loss
transmission line 6, from N2 to N3, a total of about 40 ps. On FIG. 3 the
total skew is represented by the time of the first delay time T1. A skew
this big or bigger is typical for a fast rising input clock signal along a
low loss transmission line.
This type of clock skew is typically not addressed by conventional signal
skew adjusting circuits.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by the invention which
reduces skew between clock signals by using low loss transmission lines in
conjunction with a slow rising input clock signal.
As will be discussed in further detail below, when a slow rising clock
signal is used in conjunction with a low loss transmission line 6 a period
of time or region of no apparent skew or delay exists between the clock
signals at the input and destination ends of the low loss transmission
line 6. The signals with no apparent skew or delay can be used to operate
various components within an integrated circuit.
The foregoing and other features and advantages of the invention will be
more clearly understood from the following detailed description of the
invention which is provided in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic diagram of a typical clock circuit providing multiple
clock signals to multiple destinations;
FIG. 2 is a schematic diagram of a low loss transmission line representing
a typical clock signal transmission wire;
FIG. 3 is a graph illustration of a typical fast rising input signal
propagated across a low transmission line;
FIG. 4 is a graph illustration of a slow rising input signal propagated
across a low loss transmission line;
FIG. 5 is a schematic diagram of a clock signal low loss transmission
circuit;
FIG. 6 is a schematic diagram of one embodiment of the present invention;
FIG. 7 is a schematic diagram of a second embodiment of the present
invention;
FIG. 8 is a schematic diagram of a third embodiment of the present
invention;
FIG. 9 is a schematic diagram of a fourth embodiment of the present
invention;
FIG. 10 is a schematic diagram of a fifth embodiment of the present
invention;
FIG. 11 is a graph illustration of a slow rising input signal propagated
across a low loss transmission line which creates a larger region of no
signal skew;
FIG. 12 is a diagram of a low loss transmission line in a line trench
located in an integrated circuit;
FIG. 13 is a graph showing clock signal skew for a low loss transmission
line which has a lower impedance in a shallow line trench located in an
integrated circuit;
FIG. 14 is a graph showing clock signal skew for a low loss transmission
line which has a much lower impedance in a much shallower line trench
located in an integrated circuit;
FIG. 15 illustrates in block diagram form a processor system in which a
clock signal circuit device in accordance with the present invention can
be used.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Preferred embodiments of the present invention will now be described in
conjunction with FIGS. 2-13. Other embodiments may be utilized and
structural or logical changes may be made to the described embodiments
without departing from the spirit or scope of the present invention.
One of the features of the invention is the use of a slower rising clock
signal, than what is typically used (FIG. 3). A slow rising clock signal
is a signal that rises to its maximum voltage in a longer period than it
takes the same clock signal to travel down a low loss transmission line 6
and be reflected back.
FIG. 4, is a graphical illustration of a slow rising clock signal as
launched into the FIG. 2 transmission line 6. The slow rising clock signal
is shown as signal V1, the signal V2 is the signal present at node N2, and
the signal V3 is the signal present at node N3. The input clock signal V1
rises at a slow rate, 0 volts to 5 volts in about 100 pico-seconds (ps).
The voltage V2 rises at half the rate of V1 because the V1 signal is
roughly divided in two at N2, as discussed previously. The signal V3,
rises at twice the rate as V2 because the reflected signal from the small
capacitance termination end is added to the incoming signal at N3. The
reflected signal is sent back along the low loss transmission line 6 and
adds to the voltage V2.
Point A on the FIG. 4 graph represents the point where the reflected signal
from N3 is received back at N2, causing V2 to increase. Point B on the
graph represents the point in time where the source voltage V1 reaches its
maximum value and stops increasing, therefore the input voltage to the
transmission line V2 now only consists of the reflection still arriving
back from the receiving end N3 and as a result, the rate of increase of
the voltage V2 is now reduced. This continues until all reflections have
returned from the receiving end N3 of the line.
Between point A and point B on the graph there is a period of time or
region where there is no apparent skew or delay between the signal V2 at
the sending end N2 of the low loss transmission line 6 and the signal V3
at the receiving end N3 of the low loss transmission line 6.
With reference to FIGS. 5-8, the oscillator circuit 2 and clock buffer 4
are an example of where the clock signal source might be generated. The
exemplary circuits described in FIGS. 5-8 could receive clock signals from
other destination sources, such as other circuits, as well. The methods
and techniques employed in the exemplary circuits of FIGS. 5-8 would apply
to a multitude of signals from various destination sources, including the
oscillator circuit 2 and clock buffer 4.
Referring to FIG. 5, a low loss transmission line 6 is coupled in a circuit
with an oscillator circuit 2, a clock buffer 4 with a line driver 7, and
comparators 8A, B. The comparators 8A, B are used to compare the signal at
node N2 and the signal at node N3 to a fixed reference signal V.sub.R.
Reference signal V.sub.R is merely 1/2 the output voltage of the line
driver 7. When the comparators 8A, B sample the signals at nodes N2 and N3
at a time when the input voltage exceeds the reference signal V.sub.R
voltage, there will be no delay or skew between the timing of these
sampled signals. Stated otherwise, the output signals on lines 13, 14 of
the two comparators 8A, B will have little or no skew. The output signals
on lines 13, 14 from the comparators 8A, B can be used as clock signals
for components which need clock signals or can be used as an input to
another low loss transmission line 6 for remote destination points.
FIG. 6, depicts a schematic diagram of one embodiment of the present
invention, where the end destination points D1, D2 of the clock signal are
local to the comparators 8A, B. The illustrated circuit contains an
oscillator circuit 2, a clock buffer 4 with a line driver 7, a low loss
transmission line 6, and comparators 8A, B connected to nodes N2 and N3.
The oscillator circuit 2 generates a periodic signal at a predetermined
frequency. A clock buffer 4 receives the periodic signals from oscillator
circuit 2 and generates a slow rising output clock signal. The line driver
7 propagates the slow rising clock signal down the low loss transmission
line 6 and comparator 8A, B to destination points D1, D2. By comparing the
signal at nodes N2 and N3 with the fixed reference voltage V.sub.R two
signals on lines 13, 14 with substantially no skew, that is, little or no
skew between them can be generated by the comparators and received by the
local destination points D1, D2.
FIG. 7, depicts a schematic diagram of another embodiment of the present
invention. This circuit includes an oscillator circuit 2, a clock buffer
4, multiple line drivers 7A-C, multiple low loss transmission lines 6A-C,
and multiple comparators 8A-F. The circuit diagram of FIG. 7 depicts an
embodiment for generating clock signals at multiple destination points
D1-D6, including locations remote from some of the comparators 8A-F. The
oscillator circuit 2 generates a periodic signal at a predetermined
frequency. A clock buffer 4 receives the periodic signals from oscillator
circuit 2 and generates a slow rising output clock signal. The line driver
7A propagates the slow rising clock signal down the first low loss
transmission line 6A. The signals at nodes N2 and N3 are sampled and
compared, by comparators 8A and 8B, with the fixed reference voltage
V.sub.R which produces local clock signals on lines 13A and 14A with
little or no delay. Thus, if the local clock signals are taken t points D1
and D4 there will be substantially no skew between them.
Signal 13A which is sent to a destination point D1 is also used as the
input to another low loss transmission line 6B. The new low loss
transmission line 6B has a line driver 7B, and comparators 8E, 8F. Once
again the input and termination ends of the low loss transmission line 6B
are compared to V.sub.R and two signals 13B, 13C are produced which have
substantially no skew and can be sent to various destination points such
as D3 and D5.
Signal 14A is likewise sent to a destination point D4 and is also used at
the start of another low loss transmission line 6C to reach a remote
destination point D2. The low loss transmission line 6C has an associated
line driver 7C and comparators 8C, 8D which produce signals 14B and 14C
for locations D2 and D6 which have substantially no skew. Each new
compared signal at the input and termination ends of a low loss
transmission line 6A-C can be used to feed a destination point or to start
a new low loss transmission line to a destination point in a different
location.
FIG. 8, depicts a schematic diagram of another embodiment of the present
invention where multiple signals are generated. The circuit of FIG. 8
contains an oscillator circuit 2, a clock buffer 4 which produces multiple
clock signals 45A, B, multiple line drivers 7A-F, multiple low loss
transmission lines 6A-F, and multiple comparators 8A-L. The multiple clock
signals produced by the clock buffer 4 are identical in phase and power.
The connections and methods for using the low loss transmission lines 6A-F
are the same as discussed above. Therefore, the circuit of FIG. 8 is
merely a depiction of connections and lines for sending clock signals over
two parallel paths to multiple destination points D1 though D12 with
little or no skew at the outputs of the comparators. provided at the input
and output (e.g. nodes N2 and N3 shown in FIG. 2) of each transmission
line.
When multiple low loss transmission lines are used in series, as depicted
in FIGS. 7 and 8, the input and termination ends of each low loss
transmission line have substantially no skew, but they are not necessarily
in phase with the input and termination ends of the low loss transmission
line from which it is linked. For example in FIG. 7, the clock signals at
the input and termination ends of line 6A have substantially no skew and
the clock signals at the input and termination ends of line 6B have
substantially no skew, but the clock signals of line 6A may be skewed with
respect to those of line 6B because of the transmission time through line
6B. However, this can be accounted for if all destination points require
substantially non-skewed signals. Knowing that a ramped signal is required
to drive the low loss transmission lines 6, the delay time on the signal
travelling through next low loss transmission line would be 1/2 the time
for the ramped signal. Therefore, the signals received at the destination
ends of the first low loss transmission lines in the circuit can be
delayed by a multiple of 1/2 the ramped signal so that all low loss
transmission lines 6 in the circuit have clock signals at the input and
termination ends which have substantially no skew.
FIGS. 9 and 10 are the same circuits as depicted in FIGS. 7 and 8 except
that delay circuits 20A-20D are included at the output of various
comparators 8A, 8B, 8H, and 8G leading to various destination points D1,
D4, D7 and D10. The delay circuits 20 could be used at the end of any one
of the comparators 8A-8L to provide a signal which is substantially in
phase with a transmission line within the clock circuit. The delay
circuits 20A-20D are typical delay circuits already well known and used in
circuit design.
The embodiments depicted in FIGS. 6-10 are only exemplary of circuits which
may be employed to carryout the invention. The number of destination
points and locations will ultimately determine the number of signals
produced by clock buffer 4, and the number of low loss transmission lines
6, line drivers 7, and comparators 8.
The rate at which the slow rising clock signal rises can also be varied.
FIG. 11, is a graphical illustration of the input signal V1, the signal V2
at node N2, and the signal V3 at node N3 for an even slower rising clock
signal transmitted through the circuit in FIG. 2. The input clock signal
V1 rises at an even slower rate, 0 volts to 5 volts in about 200
pico-seconds (ps), as compared with the slow rising signal previously
described and illustrated in FIG. 4, which rose from 0 volts to 5 volts in
100 ps. The voltage V2 rises at half the rate of V1 because the V1 signal
is divided at N2, as discussed previously. The clock signal V3, rises at
twice the rate as V2 because the reflected signal from the small
capacitance C.sub.L termination end is added to the incoming signal at N3.
The reflected signal is sent back along the low loss transmission line 6
and the signal is added to V2. By using an even slower rising clock signal
the region of no skew, between Points A an B, is even larger. Therefore,
there is a larger time and voltage range for the comparator 8 to sample
the signals at the input node N2 and termination node N3 of a low loss
transmission line 6.
The amount of skew between the signals at the input and termination end of
the low loss transmission line 6 is also affected by the characteristics
of the low loss transmission line 6. These characteristics include the
overall impedance of the low loss transmission line 6, the material of the
line 6, and how the line 6 is constructed.
FIG. 12, is an illustration of a typical low loss transmission line 6 and
its construction. The low loss transmission line 6 is located within a
trench 12, where the trench 12 is formed within an insulating layer 101 of
insulating material 50, of an integrated circuit. FIG. 12 shows the layer
101 as having a substrate 103 which itself may be formed of one or more
material layers. The trench 12 has a depth (h) which varies in accordance
with requirements of a particular application. The low loss transmission
line 6 can be supported by posts (not shown) or on insulator material 50
having a low k-dielectric constant such as oxide or porous oxide. Typical
low loss transmission line and trench depth dimensions, and the ones used
in determining the results of FIGS. 4 and 5, for example, are h=100 .mu.m,
with the low loss transmission line 6 had a cross section of 3.16 .mu.m by
3.16 .mu.m.
The technology of constructing low loss transmission lines 6 within a
trench 12 of an integrated circuit are discussed in several articles from
the IEEE IEDM Technical Digest of 1997 including: D. Edlestein, et al,
"Full Copper Wiring in a Sub-0.25 .mu.m CMOS ULSI Technology, p. 773-776;
S. Venkatesan, et al, "A High Performance 1.8 v, 0.2 .mu.m CMOS Technology
with Copper Metalization", p. 769-772; M. Matsuura, et al, "A Highly
Reliable Self-planarizing Low-k Intermetal Dielectric for Sub-quarter
Micron Interconnects, p. 785-788; and H. Aoki, et al, "A Degradation-free
Cu/HSQ Damascene Technology using Metal Mask Patterning and Post-CMP
Cleaning by Electrolytic Ionized Water, p. 777-781 which are all
incorporated herein by reference.
FIG. 13 depicts a slow rising input clock signal V1 propagated through the
low loss transmission line 6 where the low loss transmission line 6 is in
a shallower trench 12, h=10 .mu.m, and has a lower impedance, Zo=103 ohms
than that describe with reference to FIGS. 4 and 12. A typical impedance
of the low loss transmission line 6 is about 236 ohms, as was the case
with the impedance of the low loss transmission line 6 depicted in FIG. 4.
As can be seen in FIG. 11, there is a slightly larger clock signal delay
or skew between V2 and V3 as compared with the skew depicted in FIG. 4.
FIG. 14, depicts a slow rising clock signal input V1 propagated through a
low loss transmission line 6 with a still lower impedance, Zo=68.6 ohms
and a much shallower trench 12, h=3.16 .mu.m, as compared with the
characteristics of the low loss transmission line 6 depicted in FIG. 4.
The clock signal delay or clock skew between V2 and V3, of FIG. 14, as
compared with the skew depicted in FIG. 4 is greater. As can be seen from
FIGS. 13 and 14 the clock signal skew or delay is heavily dependant upon
the low loss transmission line 6 characteristics. Therefore, to insure
accurate timing the construction and characteristics of the line must be
considered. Typically a low loss transmission line 6 is one where the
resistance is much lower than (4L/C).sup.1/2, where L is the inductance
and C is the capacitance of the low loss transmission line 6,
R<<(4L/C).sup.1/2.
A typical processor based system which includes a clock circuit device 180
according to the present invention is illustrated generally at 100 in FIG.
15. The processor based system 100, such as a computer system, for
example, generally comprises a central processing unit (CPU) 110, for
example, a microprocessor, that communicates with one or more input/output
(I/O) devices 140, 150 over a bus 170. The computer system 100 also
includes random access memory (RAM) 160, and, in the case of a computer
system may include peripheral devices such as a floppy disk drive 120 and
a compact disk (CD) ROM drive 130 which also communicate with CPU 110 over
the bus 170. RAM 160 is preferably constructed as an integrated circuit
which includes multiple redundant columns having offset segmentation
boundaries. It may also be desirable to integrate the processor 110 and
memory 160 on a single IC chip.
Also, although the invention has been described as pertaining to reducing
clock signal skew within an integrated circuit the same method, apparatus,
and technique could be applied to interconnections within a printed
circuit board.
The above descriptions and drawings illustrate preferred embodiments which
achieve the objects, features, and advantages of the present invention. It
is not intended that the present invention be limited to the illustrated
embodiments. Any modifications of the present invention which comes within
the spirit and scope of the following claims should be considered part of
the present invention.
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