|( 1 of 261 )|
|United States Patent||6,580,154|
|Noble ,   et al.||June 17, 2003|
Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the <110> direction. Advantageously, improvements in hole carrier mobility of approximately 50% can be obtained by orienting the structure's channel in a (110) plane such that the electrical current flow is in the <110> direction. Moreover, these improved methods and structures can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity. Embodiments of a method of forming an integrated circuit include forming a trench in a silicon wafer. A trench wall of the trench has a (110) crystal plane orientation. A semiconductor device is also formed lateral to the trench wall such that the semiconductor device is capable of conducting an electrical current in a <110> direction. One method of the present invention provides for forming an integrated circuit. One method includes forming an integrated circuit including an array of MOSFETs and another method includes forming an integrated circuit including a number of lateral transistors. The present invention also includes structures as well as systems incorporating such structures all formed according to the methods provided in this application.
|Inventors:||Noble; Wendell P. (Milton, VT); Forbes; Leonard (Corvallis, OR); Reinberg; Alan R. (Westport, CT)|
|Assignee:||Micron Technology, Inc. (Boise, ID)|
|Filed:||May 8, 2001|
|Current U.S. Class:||257/627; 257/628|
|Intern'l Class:||H01L 029/04|
|Field of Search:||257/206-208,210,288,296,343,396-397,521,527,627,628|
|3999282||Dec., 1976||Ono et al.||29/571.|
|4651188||Mar., 1987||Hayashi et al.||357/38.|
|4667215||May., 1987||Kawamura et al.||357/38.|
|4768076||Aug., 1988||Aoki et al.||357/42.|
|4833516||May., 1989||Hwang et al.||257/302.|
|5196722||Mar., 1993||Bergendahl et al.||257/304.|
|5364810||Nov., 1994||Kosa et al.||437/52.|
|5371383||Dec., 1994||Miyata et al.||257/77.|
|5883012||Mar., 1999||Chiou et al.||438/748.|
|5888880||Mar., 1999||Gardner et al.||438/424.|
|5907170||May., 1999||Forbes et al.||257/296.|
|5991225||Nov., 1999||Forbes et al.||365/230.|
|6015737||Jan., 2000||Tokura et al.||438/270.|
|6066869||May., 2000||Noble et al.||257/296.|
|6072209||Jun., 2000||Noble et al.||257/296.|
|6097065||Aug., 2000||Forbes et al.||257/350.|
|6255684||Jul., 2001||Roesner et al.||257/302.|
Hodges, D.A., et al., In: Analysis and Design of Digital Integrated Circuits, Second Edition, McGraw-Hill, Inc., New York, p. 342-344, (1988).
Irene, E.A., "The Effects of Trace Amounts of Water on the Thermal Oxidation of Silicon in Oxygen", Journal of the Electrochemical Society: Solid-State Science and Technology, pp. 1613-1616, (1974).
Kim, H., et al., "The 600V Rating n-ch Trench IGBT with the Low Leakage Current and the High Channel Mobility Using the (101) Oriented Trench Sidewall", IEEE, Document No. 0-7803-3993-2/97, 265-268, (1997).
King, Y., et al., "Sub-5nm Multiple-Thickness Gate Oxide Technology Using Oxygen Implantation", IEDM Technical Digest, pp. 585-588, (1998).
Liu, C.T., et al., "Multiple Gate Oxide Thickness for 2GHz System-on-A-Chip Technologies", IEDM Technical Digest, pp. 589-592, (1998).
Petti, C.J., et al., "Characterization of Surface Mobility on the Sidewalls of Dry-Etched Trenches", IEEE IEDM '88, 104-107, (1988).
Sato, T., et al., "Drift-Velocity Saturation of Holes in Si Inversion Layers", J. Phys. Soc. Japan, 31(6), p. 1846, (1971).
Shenai, K., "A 55-V, 0.2-microohm-cm2 Vertical Trench Power MOSFET", IEEE Electron Device Letters, 12, 108-110, (Mar., 1991).
Shenai, K., "Electron Mobilities in MOS Channels Formed Along Anisotropically Dry Etched <110> Silicon Trench Sidewalls", Electronics Letters, 27, 715-717, (Apr. 25, 1991).
Theil, J.a., "Deep Trench Fabrication by Si (110) Orientation Dependent Etching", Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, Abstract, obtained from http://ojps.aip.org/>, 1 p., (Sep., 1995).
Togo, M., et al., "Multiple-Thickness Gate Oxide and Dual-Gate Technologies for High Performance Logic-Embedded DRAms", IEDM Technical Digest, pp. 347-350, (1998).
Vitkavage, S.C., et al., "An investigation of Si-SiO2 interface charges in thermally oxidized (100), (110), (111), and (511) silicon", J. Appl. Phys., 68(10), pp. 5262-5272, (1990).
Balk, P., "Orientation Dependence of Built-In Surface Charge on Thermally Oxidized Silicon", IEEE, 53, pp. 2133-2134, (1965).
Carr, W.N., et al., In: MOS/LSI Design and Application, McGraw-Hill Book Company, New York, pp. 37, 49-52, (1972).
Crowder, S., et al., "Trade-offs in the Integration of High Performance Devices with Trench Capacitor DRAM", Dig. Int. Electron Devices Meeting, Washington, D.C., pp. 45-48, (Dec. 1997).
Deal, B.E., et al., "Charateristics of the Surface-State Charge (Q) of Thermally Oxidized Silicon", J. Electrochem. Soc.: Solid State Science, pp. 266-274, (1967).