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|United States Patent||6,646,474|
|Forbes||November 11, 2003|
A logic circuit and associated method are provided to improve the switching performance of integrated circuit devices. The logic circuit includes a pass transistor logic circuit, a CMOS transistor pair connected as an inverter and having an input coupled to the output of the pass transistor logic circuit, a clocking transistor coupled between the inverter and a potential terminal to selectively enable the inverter according to a first clocking signal, and a precharge transistor coupled between the inverter output and a potential terminal to precharge the inverter output low according to a second clocking signal.
|Inventors:||Forbes; Leonard (Corvallis, OR)|
|Assignee:||Micron Technology, Inc. (Boise, ID)|
|Filed:||August 15, 2002|
|Current U.S. Class:||326/98; 326/95; 326/113; 326/17; 327/208; 327/214; 327/224|
|Intern'l Class:||H03K 019/01|
|Field of Search:||326/93,95,96,98 327/208-212,214,215,224,225|
|5841300||Nov., 1998||Murabayashi et al.|
|6046606||Apr., 2000||Chu et al.||326/95.|
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