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|United States Patent||6,664,589|
|Forbes ,   et al.||December 16, 2003|
Structure and methods for the use of PMOS devices, with p-type polysilicon gates or metal gates with large electron affinities or work functions are provided. These PMOS devices minimize tunneling leakage currents in DRAM capacitors, cells and devices, as well as conserve power supply currents to minimize power dissipation. A memory cell is provided which utilizes p-type semiconductor or metal gates or capacitor plates with work functions larger than those of n-type doped polysilicon (4.1 eV) or the commonly used aluminum metal in MOS technology (4.1 eV). The memory cell includes a PMOS transistor. The PMOS transistor includes a first source/drain region and a second source/drain region separated by a channel region. The first and the second source/drain region include source/drain regions having a large work function. The PMOS transistor has a gate opposing the channel region and separated therefrom by a gate insulator. The gate includes a gate having a large work function. The memory cell further includes a storage device, or capacitor, coupled to the second source/drain region. The capacitor includes a first storage node and a second storage node. At least one of the first and the second storage nodes includes a storage node having a large work function.
|Inventors:||Forbes; Leonard (Corvallis, OR); Akram; Salman (Boise, ID)|
|Assignee:||Micron Technology, Inc. (Boise, ID)|
|Filed:||August 30, 2001|
|Current U.S. Class:||257/328; 257/330; 257/288; 438/238; 438/197|
|Intern'l Class:||H01L 029/94|
|Field of Search:||438/238,217,197 257/328,329,330,288|
|5886368||Mar., 1999||Forbes et al.||257/77.|
|6031263||Feb., 2000||Forbes et al.||257/315.|
|6278155||Aug., 2001||Okabe et al.||257/328.|
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