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|United States Patent||6,674,167|
|Ahn ,   et al.||January 6, 2004|
Structures, systems and methods are provide for multilevel wiring interconnects in an integrated circuit assembly which alleviate problems associated with integrated circuit size and performance. The structures, systems and methods of the present invention include a method for forming multilevel wiring interconnects in an integrated circuit assembly. The method includes forming a number of multilayer metal lines separated by a number of air gaps above a substrate. A silicide layer is formed on the number of multilayer metal lines. The silicide layer is oxidized. And, a low dielectric constant insulator is deposited to fill a number of interstices created by the number of air gaps between the number of multilayer metal lines. In one embodiment, forming the number of multilayer metal lines includes a first conductor bridge level. In one embodiment, forming a silicide layer on the number of multilayer metal lines includes using a pyrolysis of silane at a temperature of between 300 and 500 degrees Celsius. Also, in one embodiment, a metal layer is formed on the oxided silicide layer. The metal layer includes a metal layer selected from the group consisting of Aluminum, Chromium, Titanium, and Zirconium. In one embodiment, the metal layer includes a layer of Aluminum oxide.
|Inventors:||Ahn; Kie Y. (Chappaqua, NY); Forbes; Leonard (Corvallis, OR); Eldridge; Jerome M. (Los Gatos, CA)|
|Assignee:||Micron Technology, Inc. (Boise, ID)|
|Filed:||May 31, 2000|
|Current U.S. Class:||257/750; 257/754; 257/758; 257/760|
|Intern'l Class:||H01L 023/48|
|Field of Search:||257/750,758,762,522,700,760,754,757|
|4762728||Aug., 1988||Keyser et al.||427/38.|
|5413962||May., 1995||Lur et al.||438/619.|
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