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|United States Patent||6,683,337|
|Forbes ,   et al.||January 27, 2004|
A method for forming edge-defined structures with sub-lithographic dimensions which are used to further form conduction channels and/or storage structures in memory cells. Sacrificial silicon nitride islands are deposited at low temperatures and then patterned and etched by high resolution etching techniques. Polysilicon is next deposited over the sacrificial silicon nitride islands and directionally etched to form edge-defined polysilicon dot and strip structures which are about one tenth the minimum feature size. The edge-defined polysilicon strips and dots are formed between the source and drain region of an NMOS device. Subsequent to the removal of the sacrificial silicon nitride islands, the edge-defined polysilicon strips and dots are used to mask a threshold voltage implantation in a conventional CMOS process. A conduction channel and two adjacent potential minimum dots are formed after the removal of the edge-defined polysilicon strips and dots.
|Inventors:||Forbes; Leonard (Corvallis, OR); Ahn; Kie Y. (Chappaqua, NY)|
|Assignee:||Micron Technology, Inc. (Boise, ID)|
|Filed:||February 9, 2001|
|Current U.S. Class:||257/215; 257/236|
|Intern'l Class:||H01L 029/76|
|Field of Search:||257/215,235,236|
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|6069380||May., 2000||Chou et al.|
|6159620||Dec., 2000||Heath et al.|
|Foreign Patent Documents|
|0 463 817||Jan., 1992||EP.|
|0 463 817||Jan., 1992||EP.|
|WO 99/66561||Dec., 1999||WO.|
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