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United States Patent | 6,734,510 |
Forbes ,   et al. | May 11, 2004 |
This invention relates to a process of forming a transistor with three vertical gate electrodes and the resulting transistor. By forming such a transistor it is possible to maintain an acceptable aspect ratio as MOSFET structures are scaled down to sub-micron sizes. The transistor gate electrodes can be formed of different materials so that the workfunctions of the three electrodes can be tailored. The three electrodes are positioned over a single channel and operate as a single gate having outer and inner gate regions.
Inventors: | Forbes; Leonard (Corvallis, OR); Tran; Luan C. (Meridian, ID); Ahn; Kie Y. (Chappaqua, NY) |
Assignee: | Micron Technology, Ing. (Boise, ID) |
Appl. No.: | 808114 |
Filed: | March 15, 2001 |
Current U.S. Class: | 257/407 |
Intern'l Class: | H01L 029/772 |
Field of Search: | 257/330,331,336,340,344,341,407,408,410,412,401,402,500,577 |
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6114736 | Sep., 2000 | Balasubramanyam et al. | |
6274510 | Aug., 2001 | Wilk et al. | |
6281559 | Aug., 2001 | Yu et al. | |
6348387 | Feb., 2002 | Yu. | |
6563151 | May., 2003 | Shin et al. |
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