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3D"[Boolean 3D[Help]=20
  (=20 1 of 572 )
United States Patent 7,154,778
Forbes December 26, 2006 =
Nanocrystal write once read only memory for archival = storage=20

Abstract

Structures and methods for write once read only memory employing = charge=20 trapping are provided. The write once read only memory cell includes a = metal=20 oxide semiconductor field effect transistor (MOSFET) in a substrate. The = MOSFET=20 has a first source/drain region, a second source/drain region, and a = channel=20 region between the first and the second source/drain regions. A gate = insulator=20 is formed opposing the channel region. The gate insulator includes a = number of=20 high work function nanoparticles. A gate is formed on the gate = insulator. A plug=20 is coupled to the first source/drain region and couples the first = source/drain=20 region to an array plate. A transmission line is coupled to the second=20 source/drain region. The MOSFET is a programmed MOSFET having a charge = trapped=20 in the number of high work function nanoparticles in the gate insulator = adjacent=20 to the first source/drain region.

Inventors: Forbes;=20 Leonard (Corvallis, OR)
Assignee: Micron=20 Technology, Inc. (Boise, ID)
Appl. No.: 11/057,634
Filed: February 14, = 2005
Related U.S. Patent Documents
Application Number Filing Date Patent Number Issue Date
10177214 Jun., 2002 6888739

Current U.S. = Class: 365/177 ; = 257/300;=20 977/938
Current International = Class:=20 G11C = 11/34 (20060101)
Field of Search: = 365/177 257/300 = 977/DIG.1,938=20

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Primary Examiner: Ho; Hoai V.=20
Attorney, Agent or Firm: Schwegman, Lundberg, Woessner = &=20 Kluth, P.A.
Parent Case Text


CROSS REFERENCE TO RELATED APPLICATIONS

The present = application=20 is a continuation of U.S. Ser. No. 10/177,214, filed Jun. 21, 2002, now = U.S.=20 Pat. No. 6,888,739, which is incorporated herein by reference in its = entirety.=20

This application is related to the following co-pending, = commonly=20 assigned U.S. patent applications: "Write Once Read Only Memory = Employing Charge=20 Trapping in Insulators," Ser. No. 10/177,077, "Write Once Read Only = Memory=20 Employing Floating Gates," Ser. No. 10/177,083,"Write Once Read Only = Memory with=20 Large Work Function Floating Gates," Ser. No. 10/177,213, "Vertical NROM = Having=20 a Storage Density of 1 Bit per 1F.sup.2," Ser. No. 10/177,208, = "Ferroelectric=20 Write Once Read Only Memory for Archival Storage," Ser. No. 10/177,082, = and=20 "Multistate NROM Having a Storage Density Much Greater than 1 Bit per = 1F.sup.2,"=20 Ser. No. 10/177,211, and each of which disclosure is herein incorporated = by=20 reference.=20
Claims


What is claimed is:

1. A memory cell, comprising: a = transistor in=20 a substrate, including: a first source/drain region; a second = source/drain=20 region; a channel region between the first and the second source/drain = regions;=20 a gate insulator formed opposing the channel region, wherein the gate = insulator=20 includes a number of charge storing nanoparticles with a work function = greater=20 that 3.2 eV, wherein the nanoparticles are within an electron tunneling = range of=20 the channel region; and a gate formed on the gate insulator.

2. = The=20 memory cell of claim 1, wherein the charge storing nanoparticles include = a work=20 function greater than 4.7 eV.

3. The memory cell of claim 1, = wherein the=20 charge storing nanoparticles include refractory metal nanoparticles. =

4.=20 The memory cell of claim 1, wherein the charge storing nanoparticles = include=20 p-type semiconductor particles.

5. The memory cell of claim 4, = wherein=20 the charge storing nanoparticles include p-type polysilicon.

6. = The=20 memory cell of claim 1, wherein the charge storing nanoparticles are not = in=20 physical contact with each other in the gate insulator.

7. A = memory=20 cell, comprising: a transistor in a substrate, including: a first = source/drain=20 region; a second source/drain region; a channel region between the first = and the=20 second source/drain regions; a gate insulator formed opposing the = channel=20 region, wherein the gate insulator includes a number of high work = function=20 nanoparticles, wherein the nanoparticles are within an electron = tunneling range=20 of the channel region; and a gate formed on the gate insulator. =

8. The=20 memory cell of claim 7, wherein the number of high work function = nanoparticles=20 includes nanoparticles with a 4.7 eV work function.

9. The = memory cell=20 of claim 7, wherein the number of high work function nanoparticles = includes=20 nanoparticles with a 5.3 eV work function.

10. A transistor, = including:=20 a first source/drain region; a second source/drain region; a channel = region=20 between the first and the second source/drain regions; a gate insulator = formed=20 opposing the channel region, wherein the gate insulator includes a = number of=20 charge storing nanoparticles within an electron tunneling range of the = channel=20 region; an electron charge stored on the nanoparticles, wherein the = electron=20 charge is stored adjacent to a source/drain region by operating the = transistor=20 in a reverse direction; and a gate formed on the gate insulator. =

11. The=20 transistor of claim 10, wherein the gate insulator includes a silicon = oxide gate=20 insulator.

12. The transistor of claim 10, wherein the second=20 source/drain region is coupled to an array plate of a memory device. =

13.=20 The transistor of claim 10, wherein the charge storing nanoparticles are = not in=20 physical contact with each other in the gate insulator.

14. The=20 transistor of claim 10, wherein the charge storing nanoparticles are = selected=20 from a group consisting of silicon germanium, silicon carbide, silicon=20 oxycarbide, gallium nitride and aluminum gallium nitride.

15. = The=20 transistor of claim 14, wherein the charge storing nanoparticles are = doped=20 p-type.

16. The transistor of claim 10, wherein the charge = storing=20 nanoparticles are selected from a group consisting of molybdenum and = tungsten.=20

17. A memory device, comprising: an array of memory cells, each = cell=20 including a transistor, including: a first source/drain region; a second = source/drain region; a channel region between the first and the second=20 source/drain regions; a gate insulator formed opposing the channel = region,=20 wherein the gate insulator includes a number of charge storing = nanoparticles=20 with a work function greater that 3.2 eV, wherein the nanoparticles are = within=20 an electron tunneling range of the channel region; a gate formed on the = gate=20 insulator; and an array plate coupled to the second source/drain regions = of the=20 memory cells in the array of memory cells.

18. The memory device = of=20 claim 17, further including circuitry to store a charge on the = nanoparticles=20 adjacent to a source/drain region by operating the transistor in a = reverse=20 direction.

19. The memory device of claim 18, further including=20 circuitry to read a memory cell by operating the transistor in a forward = direction.

20. The memory device of claim 17, wherein the charge = storing=20 nanoparticles include a work function greater than 4.7 eV.

21. = The=20 memory device of claim 17, wherein the charge storing nanoparticles = include=20 refractory metal nanoparticles.

22. The memory device of claim = 17,=20 wherein the charge storing nanoparticles include p-type semiconductor = particles.=20

23. The memory device of claim 22, wherein the charge storing=20 nanoparticles include p-type polysilicon.

24. The memory device = of claim=20 17, wherein the charge storing nanoparticles are not in physical contact = with=20 each other in the gate insulator.
=20
Description


REFERENCES

L. Forbes, W. P. Noble and E. H. Cloud, = "MOSFET=20 Technology for Programmable Address Decode and Correction," application = Ser. No.=20 09/383804, now U.S. Pat. No. 6,521,950; L. Forbes, E. Sun, R. Alders and = J.=20 Moll, "Field Induced Re-Emission of Electrons Trapped in SiO.sub.2," = IEEE Trans.=20 Electron Device, vol. ED-26, no. 11, pp. 1816 1818 (November 1979); S. = S. B. Or,=20 N. Hwang, and L. Forbes, "Tunneling and Thermal Emission From a = Distribution of=20 Deep Traps in SiO.sub.2," IEEE Trans. on Electron Devices, vol. 40, no. = 6, pp.=20 1100 1103 (June 1993); S. A. Abbas and R. C. Dockerty, "N-Channel IGFET = Design=20 Limitations Due to Hot Electron Trapping," IEEE Int. Electron Devices = Mtg.,=20 Washington D.C., December 1975, pp. 35 38). B. Eitan et al., = "Characterization=20 of Channel Hot Electron Injection by the Subthreshold Slope of NROM = device,"=20 IEEE Electron Device Lett., Vol. 22, No. 11, pp. 556 558, (November = 2001); B.=20 Etian et al., "NROM: A novel localized Trapping, 2-Bit Nonvolatile = Memory Cell,"=20 IEEE Electron Device Lett., Vol. 21, No. 11, pp. 543 545, (November = 2000); S.=20 Sze, Physics of Semiconductor Devices, Wiley, N.Y., 1981, pp. 504 506; = L. Forbes=20 and J. Geusic, "Memory Using Insulator Traps," U.S. Pat. No. 6,140,181, = issued=20 Oct. 31, 2000; C. Hu et al., "Modeling and Design Study of Nanocrystal = Memory=20 Devices," IEEE Device Research Conf., Notre Dame, Ind., June 2001, pp. = 139 140;=20 L. Forbes, "Flash Memory With Microcrystalline Silicon Carbide as the = Floating=20 Gate Structure," U.S. Pat. No. 5,801,401, issued September 1998, U.S. = Pat. No=20 5,989,958, issued 23 Nov. 1999, U.S. Pat. No. 6,166,401, Dec. 26, 2000; = L.=20 Forbes, J. Geusic and K. Ahn, "Microcrystalline Silicon Oxycarbide = Gates," U.S.=20 Pat. No. 5,886,368, issued 23 Mar. 1999; L. Forbes and K. Y. Ahn, = "DEAPROM and=20 Transistor with Gallium Nitride or Gallium Aluminum Nitride Gate," U.S. = Pat. No.=20 6,031,263, issued 29 Feb. 2000; L. Forbes, "Flash Memory with = Nanocrystalline=20 Silicon Film as the Floating Gate," U.S. Pat. No. 5,852,306, issued 22 = Dec.=20 1998.

FIELD OF THE INVENTION

The present invention = relates=20 generally to semiconductor integrated circuits and, more particularly, = to=20 nanocrystal write once read only memory for archival storage. =

BACKGROUND=20 OF THE INVENTION

Many electronic products need various amounts = of memory=20 to store information, e.g. data. One common type of high speed, low cost = memory=20 includes dynamic random access memory (DRAM) comprised of individual = DRAM cells=20 arranged in arrays. DRAM cells include an access transistor, e.g a metal = oxide=20 semiconducting field effect transistor (MOSFET), coupled to a capacitor = cell.=20 With successive generations of DRAM chips, an emphasis continues to be = placed on=20 increasing array density and maximizing chip real estate while = minimizing the=20 cost of manufacture. It is further desirable to increase array density = with=20 little or no modification of the DRAM optimized process flow.

A=20 requirement exists for memory devices which need only be programmed = once, as for=20 instance to function as an electronic film in a camera. If the memory = arrays=20 have a very high density then they can store a large number of very high = resolution images in a digital camera. If the memory is inexpensive then = it can=20 for instance replace the light sensitive films which are used to store = images in=20 conventional cameras. And, if the memory retention time is long then the = memory=20 can be used to replace microfilm and used for archival storage. =

Thus,=20 there is a need for improved DRAM technology compatible write once read = only=20 memory. It is desirable that such write once read only memory be = fabricated on a=20 DRAM chip with little or no modification of the DRAM process flow. It is = further=20 desirable that such write once read only memory operate with lower = programming=20 voltages than that used by conventional flash memory cells, yet still = hold=20 sufficient charge to withstand the effects of parasitic capacitances and = noise=20 due to circuit operation.

SUMMARY OF THE INVENTION

The = above=20 mentioned problems for creating DRAM technology compatible write once = read only=20 memory cells as well as other problems are addressed by the present = invention=20 and will be understood by reading and studying the following = specification. This=20 disclosure teaches structures and methods using MOSFET devices as write = once=20 read only memory in a DRAM integrated circuit. The structures and = methods use=20 the existing process sequence for MOSFET's in DRAM technology. =

In=20 particular, an illustrative embodiment of the present invention includes = a write=20 once read only memory cell. The write once read only memory cell = includes a=20 metal oxide semiconductor field effect transistor (MOSFET) in a = substrate. The=20 MOSFET has a first source/drain region, a second source/drain region, = and a=20 channel region between the first and the second source/drain regions. A = gate=20 insulator is formed opposing the channel region. The gate insulator = includes a=20 number of high work function nanoparticles. A gate is formed on the gate = insulator. A plug is coupled to the first source/drain region and = couples the=20 first source/drain region to an array plate. A transmission line is = coupled to=20 the second source/drain region. The MOSFET is a programmed MOSFET having = a=20 charge trapped in the number of high work function nanoparticles in the = gate=20 insulator adjacent to the first source/drain region such that the = channel region=20 has a first voltage threshold region (Vt1) and a second voltage = threshold region=20 (Vt2) and such that the programmed MOSFET operates at reduced drain = source=20 current.

These and other embodiments, aspects, advantages, and = features=20 of the present invention will be set forth in part in the description = which=20 follows, and in part will become apparent to those skilled in the art by = reference to the following description of the invention and referenced = drawings=20 or by practice of the invention. The aspects, advantages, and features = of the=20 invention are realized and attained by means of the instrumentalities,=20 procedures, and combinations particularly pointed out in the appended = claims.=20

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a block = diagram of=20 a metal oxide semiconductor field effect transistor (MOSFET) in a = substrate=20 according to the teachings of the prior art.

FIG. 1B illustrates = the=20 MOSFET of FIG. 1A operated in the forward direction showing some degree = of=20 device degradation due to electrons being trapped in the gate oxide near = the=20 drain region over gradual use.

FIG. 1C is a graph showing the = square=20 root of the current signal (Ids) taken at the drain region of the = conventional=20 MOSFET versus the voltage potential (VGS) established between the gate = and the=20 source region.

FIG. 2A is a diagram of a programmed MOSFET which = can be=20 used as a write once read only memory cell according to the teachings of = the=20 present invention.

FIG. 2B is a diagram suitable for explaining = the=20 method by which the MOSFET of the write once read only memory cell of = the=20 present invention can be programmed to achieve the embodiments of the = present=20 invention.

FIG. 2C is a graph plotting the current signal (Ids) = detected=20 at the drain region versus a voltage potential, or drain voltage, (VDS) = set up=20 between the drain region and the source region (Ids vs. VDS). =

FIG. 3=20 illustrates a portion of a memory array according to the teachings of = the=20 present invention.

FIGS. 4A 4B illustrates the operation of the = novel=20 write once read only memory cell formed according to the teachings of = the=20 present invention.

FIG. 5 illustrates the operation of a = conventional=20 DRAM cell.

FIGS. 6 and 7 illustrate the dependence of tunneling = current=20 on barrier height as applicable to the present invention.

FIG. 8 = illustrates a memory device according to the teachings of the present = invention.=20

FIG. 9 is a block diagram of an electrical system, or = processor-based=20 system, utilizing write once read only memory constructed in accordance = with the=20 present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS =

In=20 the following detailed description of the invention, reference is made = to the=20 accompanying drawings which form a part hereof, and in which is shown, = by way of=20 illustration, specific embodiments in which the invention may be = practiced. In=20 the drawings, like numerals describe substantially similar components = throughout=20 the several views. These embodiments are described in sufficient detail = to=20 enable those skilled in the art to practice the invention. Other = embodiments may=20 be utilized and structural, logical, and electrical changes may be made = without=20 departing from the scope of the present invention.

The terms = wafer and=20 substrate used in the following description include any structure having = an=20 exposed surface with which to form the integrated circuit (IC) structure = of the=20 invention. The term substrate is understood to include semiconductor = wafers. The=20 term substrate is also used to refer to semiconductor structures during=20 processing, and may include other layers that have been fabricated = thereupon.=20 Both wafer and substrate include doped and undoped semiconductors, = epitaxial=20 semiconductor layers supported by a base semiconductor or insulator, as = well as=20 other semiconductor structures well known to one skilled in the art. The = term=20 conductor is understood to include semiconductors, and the term = insulator is=20 defined to include any material that is less electrically conductive = than the=20 materials referred to as conductors. The following detailed description = is,=20 therefore, not to be taken in a limiting sense, and the scope of the = present=20 invention is defined only by the appended claims, along with the full = scope of=20 equivalents to which such claims are entitled.

FIG. 1A is useful = in=20 illustrating the conventional operation of a MOSFET such as can be used = in a=20 DRAM array. FIG. 1A illustrates the normal hot electron injection and=20 degradation of devices operated in the forward direction. As is = explained below,=20 since the electrons are trapped near the drain they are not very = effective in=20 changing the device characteristics.

FIG. 1A is a block diagram = of a=20 metal oxide semiconductor field effect transistor (MOSFET) 101 in a = substrate=20 100. The MOSFET 101 includes a source region 102, a drain region 104, a = channel=20 region 106 in the substrate 100 between the source region 102 and the = drain=20 region 104. A gate 108 is separated from the channel region 108 by a = gate oxide=20 110. A sourceline 112 is coupled to the source region 102. A bitline 114 = is=20 coupled to the drain region 104. A wordline 116 is coupled to the gate = 108.=20

In conventional operation, a drain to source voltage potential = (Vds) is=20 set up between the drain region 104 and the source region 102. A voltage = potential is then applied to the gate 108 via a wordline 116. Once the = voltage=20 potential applied to the gate 108 surpasses the characteristic voltage = threshold=20 (Vt) of the MOSFET a channel 106 forms in the substrate 100 between the = drain=20 region 104 and the source region 102. Formation of the channel 106 = permits=20 conduction between the drain region 104 and the source region 102, and a = current=20 signal (Ids) can be detected at the drain region 104.

In = operation of=20 the conventional MOSFET of FIG. 1A, some degree of device degradation = does=20 gradually occur for MOSFETs operated in the forward direction by = electrons 117=20 becoming trapped in the gate oxide 110 near the drain region 104. This = effect is=20 illustrated in FIG. 1B. However, since the electrons 117 are trapped = near the=20 drain region 104 they are not very effective in changing the MOSFET=20 characteristics.

FIG. 1C illustrates this point. FIG. 1C is a = graph=20 showing the square root of the current signal (Ids) taken at the drain = region=20 versus the voltage potential (VGS) established between the gate 108 and = the=20 source region 102. The change in the slope of the plot of SQRT Ids = versus VGS=20 represents the change in the charge carrier mobility in the channel 106. =

In FIG. 1C, .DELTA.VT represents the minimal change in the = MOSFET's=20 threshold voltage resulting from electrons gradually being trapped in = the gate=20 oxide 110 near the drain region 104, under normal operation, due to = device=20 degradation. This results in a fixed trapped charge in the gate oxide = 110 near=20 the drain region 104. Slope 103 represents the charge carrier mobility = in the=20 channel 106 for FIG. 1A having no electrons trapped in the gate oxide = 110. Slope=20 105 represents the charge mobility in the channel 106 for the = conventional=20 MOSFET of FIG. 1B having electrons 117 trapped in the gate oxide 110 = near the=20 drain region 104. As shown by a comparison of slope 103 and slope 105 in = FIG.=20 1C, the electrons 117 trapped in the gate oxide 110 near the drain = region 104 of=20 the conventional MOSFET do not significantly change the charge mobility = in the=20 channel 106.

There are two components to the effects of stress = and hot=20 electron injection. One component includes a threshold voltage shift due = to the=20 trapped electrons and a second component includes mobility degradation = due to=20 additional scattering of carrier electrons caused by this trapped charge = and=20 additional surface states. When a conventional MOSFET degrades, or is=20 "stressed," over operation in the forward direction, electrons do = gradually get=20 injected and become trapped in the gate oxide near the drain. In this = portion of=20 the conventional MOSFET there is virtually no channel underneath the = gate oxide.=20 Thus the trapped charge modulates the threshold voltage and charge = mobility only=20 slightly.

The inventor, along with others, has previously = described=20 programmable memory devices and functions based on the reverse stressing = of=20 MOSFET's in a conventional CMOS process and technology in order to form=20 programmable address decode and correction in U.S. Pat. No. 6,521,950 = entitled=20 "MOSFET Technology for Programmable Address Decode and Correction". That = disclosure, however, did not describe write once read only memory = solutions, but=20 rather address decode and correction issues.

According to the = teachings=20 of the present invention, normal MOSFETs can be programmed by operation = in the=20 reverse direction and utilizing avalanche hot electron injection to trap = electrons in a number of high work function nanoparticles, or = nanocrystals,=20 within a gate oxide of the MOSFET. When the programmed MOSFET is = subsequently=20 operated in the forward direction the electrons, trapped in the number = of high=20 work function nanoparticles, or nanocrystals, within the gate oxide, are = near=20 the source and cause the channel to have two different threshold voltage = regions. The novel programmed MOSFETs of the present invention conduct=20 significantly less current than conventional MOSFETs, particularly at = low drain=20 voltages. These electrons will remain trapped in the number of high work = function nanoparticles, or nanocrystals, within the gate oxide gate = unless=20 negative gate voltages are applied. The electrons will not be removed = from the=20 number of high work function nanoparticles, or nanocrystals, within a = gate oxide=20 when positive or zero gate voltages are applied. Erasure can be = accomplished by=20 applying negative gate voltages and/or increasing the temperature with = negative=20 gate bias applied to cause the trapped electrons to be re-emitted back = into the=20 silicon channel of the MOSFET.

FIGS. 2A 2C illustrate are useful = in=20 illustrating the present invention in which a much larger change in = device=20 characteristics is obtained by programming the device in the reverse = direction=20 and subsequently reading the device by operating it in the forward = direction.=20

FIG. 2A is a diagram of a programmed MOSFET which can be used as = a write=20 once read only memory cell according to the teachings of the present = invention.=20 As shown in FIG. 2A the write once read only memory cell 201 includes a = MOSFET=20 in a substrate 200 which has a first source/drain region 202, a second=20 source/drain region 204, and a channel region 206 between the first and = second=20 source/drain regions, 202 and 204. In one embodiment, the first = source/drain=20 region 202 includes a source region 202 for the MOSFET and the second=20 source/drain region 204 includes a drain region 204 for the MOSFET. FIG. = 2A=20 further illustrates a gate 208 separated from the channel region 206 by = a gate=20 oxide 210. According to the teachings of the present invention, a number = of high=20 work function nanoparticles, or nanocrystals, 240 are located within the = gate=20 oxide 210. A first transmission line 212 is coupled to the first = source/drain=20 region 202 and a second transmission line 214 is coupled to the second=20 source/drain region 204. In one embodiment, the first transmission line = includes=20 a sourceline 212 and the second transmission line includes a bit line = 214.=20

As stated above, write once read only memory cell 201 is = comprised of a=20 programmed MOSFET. This programmed MOSFET has a charge 217 trapped in = the number=20 of high work function nanoparticles, or nanocrystals, 240 within the = gate oxide=20 210 adjacent to the first source/drain region 202 such that the channel = region=20 206 has a first voltage threshold region (Vt1) and a second voltage = threshold=20 region (Vt2) in the channel 206. In one embodiment, the charge 217 = trapped in=20 the number of high work function nanoparticles, or nanocrystals, 240 = within the=20 gate oxide 210 adjacent to the first source/drain region 202 includes a = trapped=20 electron charge 217.

FIG. 2A illustrates the Vt2 in the channel = 206 is=20 adjacent the first source/drain region 202 and that the Vt1 in the = channel 206=20 is adjacent the second source/drain region 204. According to the = teachings of=20 the present invention, Vt2 has a higher voltage threshold than Vt1 due = to the=20 charge 217 trapped in the number of high work function nanoparticles, or = nanocrystals, 240 within a gate oxide 210 adjacent to the first = source/drain=20 region 202.

FIG. 2B is a diagram suitable for explaining the = method by=20 which the MOSFET of the write once read only memory cell 201 of the = present=20 invention can be programmed to achieve the embodiments of the present = invention.=20 As shown in FIG. 2B the method includes programming the MOSFET in a = reverse=20 direction. Programming the MOSFET in the reverse direction includes = applying a=20 first voltage potential V1 to a drain region 204 of the MOSFET. In one=20 embodiment, applying a first voltage potential V1 to the drain region = 204 of the=20 MOSFET includes grounding the drain region 204 of the MOSFET as shown in = FIG.=20 2B. A second voltage potential V2 is applied to a source region 202 of = the=20 MOSFET. In one embodiment, applying a second voltage potential V2 to the = source=20 region 202 includes applying a high positive voltage potential (VDD) to = the=20 source region 202 of the MOSFET, as shown in FIG. 2B. A gate potential = VGS is=20 applied to a gate 208 of the MOSFET. In one embodiment, the gate = potential VGS=20 includes a voltage potential which is less than the second voltage = potential V2,=20 but which is sufficient to establish conduction in the channel 206 of = the MOSFET=20 between the drain region 204 and the source region 202. As shown in FIG. = 2B,=20 applying the first, second and gate potentials (V1, V2, and VGS = respectively) to=20 the MOSFET creates a hot electron injection into a number of high work = function=20 nanoparticles, or nanocrystals, 240 within the gate oxide 210 of the = MOSFET=20 adjacent to the source region 202. In other words, applying the first, = second=20 and gate potentials (V1, V2, and VGS respectively) provides enough = energy to the=20 charge carriers, e.g. electrons, being conducted across the channel 206 = that,=20 once the charge carriers are near the source region 202, a number of the = charge=20 carriers get excited into the number of high work function = nanoparticles, or=20 nanocrystals, 240 within the gate oxide 210 adjacent to the source = region 202.=20 Here the charge carriers become trapped.

In one embodiment of = the=20 present invention, the method is continued by subsequently operating the = MOSFET=20 in the forward direction in its programmed state during a read = operation.=20 Accordingly, the read operation includes grounding the source region 202 = and=20 precharging the drain region a fractional voltage of VDD. If the device = is=20 addressed by a wordline coupled to the gate, then its conductivity will = be=20 determined by the presence or absence of stored charge in the number of = high=20 work function nanoparticles, or nanocrystals, 240 within the gate oxide = 210.=20 That is, a gate potential can be applied to the gate 208 by a wordline = 216 in an=20 effort to form a conduction channel between the source and the drain = regions as=20 done with addressing and reading conventional DRAM cells. =

However, now=20 in its programmed state, the conduction channel 206 of the MOSFET will = have a=20 first voltage threshold region (Vt1) adjacent to the drain region 204 = and a=20 second voltage threshold region (Vt2) adjacent to the source region 202, = as=20 explained and described in detail in connection with FIG. 2A. According = to the=20 teachings of the present invention, the Vt2 has a greater voltage = threshold than=20 the Vt1 due to the hot electron injection 217 into a number of high work = function nanoparticles, or nanocrystals, 240 within the gate oxide 210 = of the=20 MOSFET adjacent to the source region 202.

FIG. 2C is a graph = plotting a=20 current signal (Ids) detected at the second source/drain region 204 = versus a=20 voltage potential, or drain voltage, (VDS) set up between the second=20 source/drain region 204 and the first source/drain region 202 (Ids vs. = VDS). In=20 one embodiment, VDS represents the voltage potential set up between the = drain=20 region 204 and the source region 202. In FIG. 2C, the curve plotted as = 205=20 represents the conduction behavior of a conventional MOSFET where the = MOSFET is=20 not programmed (is normal or not stressed) according to the teachings of = the=20 present invention. The curve 207 represents the conduction behavior of = the=20 programmed MOSFET (stressed), described above in connection with FIG. = 2A,=20 according to the teachings of the present invention. As shown in FIG. = 2C, for a=20 particular drain voltage, VDS, the current signal (IDS2) detected at the = second=20 source/drain region 204 for the programmed MOSFET (curve 207) is = significantly=20 lower than the current signal (IDS1) detected at the second source/drain = region=20 204 for the conventional MOSFET (curve 205) which is not programmed = according to=20 the teachings of the present invention. Again, this is attributed to the = fact=20 that the channel 206 in the programmed MOSFET of the present invention = has two=20 voltage threshold regions and that the voltage threshold, Vt2, near the = first=20 source/drain region 202 has a higher voltage threshold than Vt1 near the = second=20 source/drain region due to the charge 217 trapped in the number of high = work=20 function nanoparticles, or nanocrystals, 240 within the gate oxide 210 = adjacent=20 to the first source/drain region 202.

Some of these effects have = recently been described for use in a different device structure, called = an NROM,=20 for flash memories. This latter work in Israel and Germany is based on = employing=20 charge trapping in a silicon nitride layer in a non-conventional flash = memory=20 device structure. Charge trapping in silicon nitride gate insulators was = the=20 basic mechanism used in MNOS memory devices, charge trapping in aluminum = oxide=20 gates was the mechanism used in MIOS memory devices, and the present = inventors=20 have previously disclosed charge trapping at isolated point defects in = gate=20 insulators.

In contrast to the above work, the present invention = discloses programming a MOSFET in a reverse direction to trap charge in = a number=20 of high work function nanoparticles, or nanocrystals, 240 within a gate = oxide=20 210 near the source region 202 and reading the device in a forward = direction to=20 form a write once memory based on a modification of DRAM technology.=20

Prior art DRAM technology generally employs silicon oxide as the = gate=20 insulator. Further the emphasis in conventional DRAM devices is placed = on trying=20 to minimize charge trapping in the silicon oxide gate insulator. = According to=20 the teachings of the present invention, a number of high work function=20 nanoparticles, or nanocrystals, within a gate oxide are used to trap = electrons=20 more efficiently than in silicon oxide. That is, in the present = invention, the=20 write-once-read-only-memory (WOROM) employs charge trapping in a number = of high=20 work function nanoparticles, or nanocrystals, within a gate oxide. = According to=20 the teachings of the present invention, the number of high work function = nanoparticles, or nanocrystals, include refractory metal nanoparticles = isolated=20 from each other and electrically floating to act as floating gates. In = one=20 embodiment, the refractory metal nanoparticles are selected from the = group of=20 molybdenum (Mo) and tungsten (W) with work functions of approximately = 4.7 eV. In=20 another embodiment of the present invention, the number of high work = function=20 nanoparticles include large work function nanocrystals selected from the = group=20 of p-type nanocrystals of silicon germanium for gates, p-type = nanocrystals gates=20 of other semiconductors as silicon carbide, silicon oxycarbide, gallium = nitride=20 (GaN), and aluminum gallium nitride (AlGaN). Again, the nanocrystals are = isolated from one another and not in conductive contact. In still other=20 embodiments according to the present invention, the number of high work = function=20 nanoparticles include heavily doped p-type polysilicon floating and = isolated=20 nanocrystals with a vacuum work function of 5.3 eV.

FIG. 3 = illustrates a=20 portion of a memory array 300 according to the teachings of the present=20 invention. The memory in FIG. 3, is shown illustrating a pair of write = once read=20 only memory cells 301-1 and 301-2 formed according to the teachings of = the=20 present invention. As one of ordinary skill in the art will understand = upon=20 reading this disclosure, any number of write once and read only memory = cells can=20 be organized in an array, but for ease of illustration only two are = displayed in=20 FIG. 3. As shown in FIG. 3, a first source/drain region, 302-1 and 302-2 = respectively, is coupled to an array plate 304. A second source/drain = region,=20 306-1 and 306-2 respectively, is coupled to a bitline, 308-1 and 308-2=20 respectively. Each of the bitlines, 308-1 and 308-2, couple to a sense=20 amplifier, shown generally at 310. A wordline, 312-1 and 312-2 = respectively, is=20 couple to a gate, 314-1 and 314-2 respectively, for each of the write = once read=20 only memory cells, 301-1 and 301-2. Finally, a write data/precharge = circuit is=20 shown at 324 for coupling a first or a second potential to bitline = 308-1. The=20 illustrated write data/precharge circuit 324 is connected to a write=20 data/precharge control line 325. As one of ordinary skill in the art = will=20 understand upon reading this disclosure, the write data/precharge = circuit 324 is=20 adapted to couple either a ground to the bitline 308-1 during a write = operation=20 in the reverse direction, or alternatively to precharge the bitline = 308-1 to=20 fractional voltage of VDD during a read operation in the forward = direction. As=20 one of ordinary skill in the art will understand upon reading this = disclosure,=20 the array plate 304 can be biased to a voltage higher than VDD during a = write=20 operation in the reverse direction, or alternatively grounded during a = read=20 operation in the forward direction.

As shown in FIG. 3, the = array=20 structure 300, including write once read only memory cells 301-1 and = 301-2, has=20 no capacitors. Instead, according to the teachings of the present = invention, the=20 first source/drain region or source region, 302-1 and 302-2, are coupled = via a=20 conductive plug directly to the array plate 304. In order to write, the = array=20 plate 304 is biased to voltage higher than VDD and the devices stressed = in the=20 reverse direction by grounding the data or bit line, 308-1 or 308-2. If = the=20 write once read only memory cell, 301-1 or 301-2, is selected by a word = line=20 address, 312-1 or 312-2, then the write once read only memory cell, = 301-1 or=20 301-2, will conduct and be stressed with accompanying hot electron = injection=20 into a number of high work function nanoparticles, or nanocrystals, 340 = within a=20 gate oxide 310 adjacent to the source region, 302-1 or 302-2. During = read the=20 write once read only memory cells, 301-1 or 301-2, are operated in the = forward=20 direction with the array plate 304 grounded and the bit line, 308-1 or = 308-2,=20 and respective second source/drain region or drain region, 306-1 and = 306-2, of=20 the cells precharged to some fractional voltage of Vdd. If the device is = addressed by the word line, 312-1 or 312-2, then its conductivity will = be=20 determined by the presence or absence of stored charge in the number of = high=20 work function nanoparticles, or nanocrystals, within a gate oxide = adjacent to=20 the source region, 302-1 or 302-2 and so detected using the DRAM sense = amplifier=20 310. The operation of DRAM sense amplifiers is described, for example, = in U.S.=20 Pat. Nos. 5,627,785; 5,280,205; and 5,042,011, all assigned to Micron = Technology=20 Inc., and incorporated by reference herein. The array would thus be = addressed=20 and read in the conventional manner used in DRAM's, but programmed as = write once=20 read only memory cells in a novel fashion.

In operation the = devices=20 would be subjected to hot electron stress in the reverse direction by = biasing=20 the array plate 304, and read while grounding the array plate 304 to = compare a=20 stressed write once read only memory cell, e.g. cell 301-1, to an = unstressed=20 dummy device/cell, e.g. 301-2, as shown in FIG. 3. The write and = possible erase=20 feature could be used during manufacture and test to initially program = all cells=20 or devices to have similar or matching conductivity before use in the = field. The=20 sense amplifier 310 can then detect small differences in cell or device=20 characteristics due to stress induced changes in device characteristics = during=20 the write operation. That is the sense amplifier 310 can detect a charge = trapped=20 in the number of high work function nanoparticles, or nanocrystals, 340 = within a=20 gate oxide 310 adjacent to the source region, 302-1 or 302-2.

As = one of=20 ordinary skill in the art will understand upon reading this disclosure = such=20 arrays of write once read only memory cells are conveniently realized by = a=20 modification of DRAM technology. As stated above and according to the = teachings=20 of the present invention, the number of high work function = nanoparticles, or=20 nanocrystals, include refractory metal nanoparticles isolated from each = other=20 and electrically floating to act as floating gates. In one embodiment, = the=20 refractory metal nanoparticles are selected from the group of molybdenum = (Mo)=20 and tungsten (W) with work functions of approximately 4.7 eV. In another = embodiment of the present invention, the number of high work function=20 nanoparticles include large work function nanocrystals selected from the = group=20 of p-type nanocrystals of silicon germanium for gates, p-type = nanocrystals gates=20 of other semiconductors as silicon carbide, silicon oxycarbide, gallium = nitride=20 (GaN), and aluminum gallium nitride (AlGaN). Again, the nanocrystals are = isolated from one another and not in conductive contact. In still other=20 embodiments according to the present invention, the number of high work = function=20 nanoparticles include heavily doped p-type polysilicon floating and = isolated=20 nanocrystals with a vacuum work function of 5.3 eV. Conventional = transistors for=20 address decode and sense amplifiers can be fabricated after this step = with=20 normal thin gate insulators of silicon oxide.

FIGS. 4A B and 5 = are=20 useful in illustrating the use of charge storage in a number of high = work=20 function nanoparticles, or nanocrystals, within a gate oxide to modulate = the=20 conductivity of the write once read only memory cell according to the = teachings=20 of the present invention. That is, FIGS. 4A 4B illustrates the operation = of the=20 novel write once read only memory cell 401 formed according to the = teachings of=20 the present invention. And, FIG. 5 illustrates the operation of a = conventional=20 DRAM cell 501. As shown in FIG. 4A, the gate insulator 410 is made = thicker than=20 in a conventional DRAM cell. For example, an embodiment of the gate = insulator=20 410 has a thickness 411 equal to or greater than 10 nm or 100 .ANG. = (10.sup.-6=20 cm). And, the gate insulator 410 includes a number of high work function = nanoparticles, or nanocrystals, 440 formed therein which are isolated = from each=20 other and electrically floating, e.g. not in conductive contact, to act = as=20 floating gates. In the embodiment shown in FIG. 4A a write once read = only memory=20 cell has dimensions 413 of 0.1 .mu.m (10.sup.-5 cm) by 0.1 .mu.m. The=20 capacitance, Ci, of the structure depends on the dielectric constant,=20 .epsilon..sub.i, and the thickness of the insulating layers, t. In an=20 embodiment, the dielectric constant is 0.3.times.10.sup.-12 F/cm and the = thickness of the insulating layer is 10.sup.-6 cm such that = Ci=3D.epsilon.i/t,=20 Farads/cm.sup.2 or 3.times.10.sup.-7 F/cm.sup.2. In one embodiment, a = charge 417=20 of 10.sup.12 electrons/cm.sup.2 is programmed into the number of high = work=20 function nanoparticles, or nanocrystals, 440 within the gate oxide 410 = adjacent=20 to the source region 402 of the write once read only memory cell 401. = This=20 produces a stored charge .DELTA.Q=3D10.sup.12=20 electrons/cm.sup.2.times.1.6.times.10.sup.-19 Coulombs. In this = embodiment, the=20 resulting change in the threshold voltage (.DELTA.Vt) of the write once = read=20 only memory cell 401 will be approximately 0.5 Volts = (.DELTA.Vt=3D.DELTA.Q/Ci or=20 1.6.times.10.sup.-7/3.times.10.sup.-7=3D1/2 Volt). In effect, the = programmed write=20 once read only memory cell, or modified MOSFET is a programmed MOSFET = having a=20 charge 417 trapped in the number of high work function nanoparticles, or = nanocrystals, 440 within the gate oxide 410 adjacent to the first = source/drain=20 region, or source region, 402 such that the channel region has a first = voltage=20 threshold region (Vt1) and a second voltage threshold region (Vt2), = where Vt2 is=20 greater than Vt1, and Vt2 is adjacent the source region 402 such that = the=20 programmed MOSFET operates at reduced drain source current. For=20 .DELTA.Q=3D10.sup.12 electrons/cm.sup.3 in an area of 10.sup.-10 = cm.sup.2, this=20 embodiment of the present invention involves trapping a charge 417 of=20 approximately 100 electrons in the number of high work function = nanoparticles,=20 or nanocrystals, 440 within the gate oxide 410 adjacent to the source = region 402=20 of the write once read only memory cell 401. In this embodiment, an = original=20 V.sub.T is approximately 1/2 Volt and the V.sub.T with charge trapping = is=20 approximately 1 Volt.

FIG. 4B aids to further illustrate the = conduction=20 behavior of the novel write once read only memory cell of the present = invention.=20 As one of ordinary skill in the art will understand upon reading this=20 disclosure, if the write once read only memory cell is being driven with = a=20 control gate 416 voltage of 1.0 Volt (V) and the nominal threshold = voltage=20 without the number of high work function nanoparticles, or nanocrystals, = 440=20 within the gate oxide 410 adjacent to the source region 402 charged is = 1/2 V,=20 then if the number of high work function nanoparticles, or nanocrystals, = 440=20 within the gate oxide 410 adjacent to the source region 402 is charged = the=20 transistor of the present invention will be off and not conduct. That = is, by=20 trapping a charge 417 of approximately 100 electrons in the number of = high work=20 function nanoparticles, or nanocrystals, 440 within the gate oxide 410 = adjacent=20 to the source region 402 of the write once read only memory cell 401, = having=20 dimensions of 0.1 .mu.m (10.sup.-5 cm) by 0.1 .mu.m, will raise the = threshold=20 voltage of the write once read only memory cell to 1.0 Volt and a 1.0 = Volt gate=20 potential will not be sufficient to turn the device on, e.g. Vt=3D1.0 V, = I=3D0.=20

Conversely, if the nominal threshold voltage without the number = of high=20 work function nanoparticles, or nanocrystals, 440 within the gate oxide = 410=20 adjacent to the source region 402 charged is 1/2 V, then=20 I=3D.mu.C.sub.ox.times.(W/L).times.((Vgs-Vt).sup.2/2), or 12.5 .mu.A, = with=20 .mu.C.sub.ox=3D.mu.C.sub.i=3D100 .mu.A/V.sup.2 and W/L=3D1. That is, the = write once=20 read only memory cell of the present invention, having the dimensions = describe=20 above will produce a current I=3D100 = .mu.A/V.sup.2.times.(1/4).times.(1/2)=3D12.5=20 .mu.A. Thus, in the present invention an unwritten, or unprogrammed = write once=20 read only memory cell can conduct a current of the order 12.5 uA, = whereas if the=20 number of high work function nanoparticles, or nanocrystals, 440 within = the gate=20 oxide 410 adjacent to the source region 402 is charged then the write = once read=20 only memory cell will not conduct.

As one of ordinary skill in = the art=20 will understand upon reading this disclosure, the sense amplifiers used = in DRAM=20 arrays, and as describe above, can easily detect such differences in = current on=20 the bit lines.

By way of comparison, in a conventional DRAM cell = 550=20 with a 30 femtoFarad (fF) storage capacitor 551 charged to 50 femto = Coulombs=20 (fC), if these are read over 5 nS then the average current on a bit line = 552 is=20 only 10 .mu.A (I=3D50 fC/5 ns=3D10 .mu.A). Thus, storing a 50 fC charge = on the=20 storage capacitor shown in FIG. 5 equates to storing 300,000 electrons = (Q=3D50=20 fC/(1.6.times.10.sup.-19)=3D30.times.10.sup.4=3D300,000 electrons).=20

According to the teachings of the present invention, the = transistors in=20 the array are utilized not just as passive on or off switches as = transfer=20 devices in DRAM arrays but rather as active devices providing gain. In = the=20 present invention, to program the transistor "off," requires only a = stored=20 charge 417 in the number of high work function nanoparticles, or = nanocrystals,=20 440 within the gate oxide 410 adjacent to the source region 402 of only = about=20 100 electrons if the area is 0.1 .mu.m by 0.1 .mu.m. And, if the write = once read=20 only memory cell is un-programmed, e.g. no stored charge trapped in the = number=20 of high work function nanoparticles, or nanocrystals, 440 within the = gate oxide=20 410 adjacent to the source region 402, and if the transistor is = addressed, via=20 control gate 416, over 10 nS a of current of 12.5 .mu.A is provided. The = integrated drain 404 current then has a charge of 125 fC or 800,000 = electrons.=20 This is in comparison to the charge on a DRAM capacitor of 50 fC which = is only=20 about 300,000 electrons. Hence, the use of the transistors in the array = as=20 active devices with gain, rather than just switches, provides an = amplification=20 of the stored charge, in the number of high work function nanoparticles, = or=20 nanocrystals, 440 within the gate oxide 410 adjacent to the source = region 402,=20 from 100 to 800,000 electrons over a read address period of 10 nS. =

The=20 unique aspect of this disclosure is the use of nanocrystals, or = nanoparticles=20 isolated from each other and electrically floating to act as floating = gates with=20 large work functions to increase the tunneling barriers with the silicon = oxide=20 gate insulators on each side of these nanocrystals or nanoparticles, as = shown in=20 FIG. 4A. Current flash memories utilize a floating polysilicon gate over = a=20 silicon dioxide gate insulator of thickness of the order 100 .ANG. or 10 = nm or=20 less in a field effect transistor. This results in a high barrier = energy, as=20 shown in FIGS. 6 and 7 , of around 3.2 eV for electrons between the = silicon=20 substrate and gate insulator and between the floating polysilicon gate = and=20 silicon oxide gate insulators. This combination of barrier height and = oxide=20 thickness results in long retention times even at 250 degrees Celsius. = The=20 simple idea would be that retention times are determined by thermal = emission=20 over the 3.2 eV barrier, however, these are extremely long so the = current model=20 is that retention is limited by F-N tunneling off of the charged gate. = This=20 produces a lower "apparent" activation energy of 1.5 eV as has been = observed and=20 shorter retention times. For archival storage in a write once mode of = operation=20 with no requirement to erase the longest possible retention times will = be=20 achieved with a number of high work function nanoparticles, or = nanocrystals,=20 440, e.g. having work functions larger than 3.2 eV, within the gate = oxide 410.=20 FIG. 7 provides a chart showing the dependence of tunneling current on = barrier=20 height. FIG. 7 illustrates a number of different electric fields E1, E2, = and E3=20 plotted for the log of various tunneling current density (A/cm.sup.2) = versus=20 various barrier energy, .PHI., (eV). The same is also described in a = copending=20 application by the same inventor and filed on even data herewith, = entitled,=20 "Write Once Read Only Memory with Large Work Function Floating gates,"=20 application Ser. No. 10/177,213, which is hereby incorporated in full by = specific reference.

The design considerations involved for the = retention=20 time of silicon nanoparticles were recently outlined in simulations = based on the=20 size of the nanoparticles and the gate insulator thickness. The = nanoparticles=20 440 as shown in FIG. 4A, should be of the order 50 .ANG. to avoid = quantum=20 confinement effects, the gate insulator 410 should be of the order 50 = .ANG. or=20 preferably thicker, and the read voltages low, of the order 2.0 Volts or = less.=20 This combined with the use of nanoparticles with large work functions = 440 will=20 provide retention times without any applied bias of the order 10.sup.15 = seconds,=20 or a million years. The practical retention time will be limited and = determined=20 by the number of read cycles but will still be archival.

The = inventor in=20 the present case has previously described the use of charge trapping on=20 nanoparticles acting as floating gates in field effect transistors. (See = generally, L. Forbes, "A MULTI-STATE FLASH MEMORY CELL AND METHOD FOR=20 PROGRAMMING SINGLE ELECTRON DIFFERENCES," U.S. Pat. No. 5,740,104, = issued 14=20 Apr. 1998; K. Y. Ahn and L. Forbes, "SINGLE ELECTRON MOSFET MEMORY = DEVICE," U.S.=20 Pat. No. 6,125,062, issued Sep. 26, 2000; K. Y. Ahn and L. Forbes, = "SINGLE=20 ELECTRON RESISTOR MEMORY DEVICE AND METHOD FOR USE THEREOF," U.S. Pat. = No.=20 6,141,260, issued Oct. 31, 2000; and L. Forbes and K. Y. Ahn, "DYNAMIC = MEMORY=20 BASED ON SINGLE ELECTRON STORAGE," application Ser. No. 09/779,547, = filed Feb.=20 9, 2001). All of the above listed references share a common ownership = with the=20 present disclosure at the time of invention. In contrast to the above = work, this=20 disclosure describes the use of nanoparticles with large work functions = 440=20 buried in thick gate insulators 410 to provide extremely long retention = times=20 and archival storage. This is done at the expense of allowing for ease = of erase=20 of the stored charge, not an important consideration in write once = memory=20 applications, and at the expense of large detection signals, which is=20 compensated for here by DRAM like arrays and comparing the sensed device = to a=20 dummy cell as is done in DRAM's. (See FIG. 3).

According to the=20 teachings of the present invention, retention times will be increased by = using:=20 (i) thick gate insulators between the silicon substrate and nanocrystal = gates,=20 since there is no requirement for erase lower electric fields result in = lower=20 tunneling currents and longer retention, see FIG. 6 (ii) thick gate = insulators=20 between the nanocrystals and address or control gate; since there is no=20 requirement for erase lower electric fields result in longer retention = times=20 (iii) low read voltages on the address or control gates; since the DRAM = sense=20 amplifiers can sense small differences in conductivity states smaller = biases can=20 be applied to the devices resulting in lower electric fields and longer=20 retention times This disclosure then describes the use of: (i) = refractory metal=20 nanoparticles isolated from each other and electrically floating to act = as=20 floating gates, Mo and W, with vacuum work functions of around 4.7 eV = which is=20 larger than that of conventional n-type polysilicon floating gates with = a vacuum=20 work function of 4.1 eV, larger barriers result in lower tunneling = currents and=20 longer retention times, see FIG. 7 and the above cited references (ii) = heavily=20 doped p-type polysilicon floating and isolated nanocrystals with a = vacuum work=20 function of 5.3 eV, p-type nanocrystals of silicon-germanium for gates, = or=20 p-type nanocrystal gates of other semiconductors as silicon carbide, = silicon=20 oxycarbide, and GaN or AlGaN with vacuum work functions greater than=20 conventional n-type polysilicon floating gates. Examples for the same, = can be=20 found in a number of patents issued to the same inventor; L. Forbes, = "FLASH=20 MEMORY WITH MICROCRYSTALLINE SILICON CARBIDE AS THE FLOATING GATE = STRUCTURE,"=20 U.S. Pat. No. 5,801,401, 1 issued September 1998, U.S. Pat. No. = 5,989,958,=20 issued 23 Nov. 1999, U.S. Pat. No. 6,166,401, Dec. 26, 2000; L. Forbes, = J.=20 Geusic and K. Ahn, "MICROCRYSTALLINE SILICON OXYCARBIDE GATES," U.S. = Pat. No.=20 5,886,368, issued 23 Mar. 1999; L. Forbes and K. Y. Ahn, "DEAPROM AND = TRANSISTOR=20 WITH GALLIUM NITRIDE OR GALLIUM ALUMINUM NITRIDE GATE," U.S. Pat. No. = 6,031,263,=20 issued 29 Feb. 2000. The nanocrystals here are isolated crystal not in=20 conductive contact with each other. Examples for the same, can be found = in=20 another patent issued to the same inventor; L. Forbes, "FLASH MEMORY = WITH=20 NANOCRYSTALLINE SILICON FILM AS THE FLOATING GATE," U.S. Pat. No. = 5,852,306,=20 issued 22 Dec. 1998. All of the above listed references share a common = ownership=20 with the present disclosure at the time of invention. In contrast to the = above=20 work, this disclosure describes the use of nanoparticles with large work = function buried in thick gate insulators to provide extremely long = retention=20 times and archival storage.

In FIG. 8 a memory device is = illustrated=20 according to the teachings of the present invention. The memory device = 840=20 contains a memory array 842, row and column decoders 844, 848 and a = sense=20 amplifier circuit 846. The memory array 842 consists of a plurality of = write=20 once read only memory cells 800, formed according to the teachings of = the=20 present invention whose word lines 880 and bit lines 860 are commonly = arranged=20 into rows and columns, respectively. The bit lines 860 of the memory = array 842=20 are connected to the sense amplifier circuit 846, while its word lines = 880 are=20 connected to the row decoder 844. Address and control signals are input = on=20 address/control lines 861 into the memory device 840 and connected to = the column=20 decoder 848, sense amplifier circuit 846 and row decoder 844 and are = used to=20 gain read and write access, among other things, to the memory array 842. =

The column decoder 848 is connected to the sense amplifier = circuit 846=20 via control and column select signals on column select lines 862. The = sense=20 amplifier circuit 846 receives input data destined for the memory array = 842 and=20 outputs data read from the memory array 842 over input/output (I/O) data = lines=20 863. Data is read from the cells of the memory array 842 by activating a = word=20 line 880 (via the row decoder 844), which couples all of the memory = cells=20 corresponding to that word line to respective bit lines 860, which = define the=20 columns of the array. One or more bit lines 860 are also activated. When = a=20 particular word line 880 and bit lines 860 are activated, the sense = amplifier=20 circuit 846 connected to a bit line column detects and amplifies the = conduction=20 sensed through a given write once read only memory cell, where in the = read=20 operation the source region of a given cell is couple to a grounded = array plate=20 (not shown), and transfered its bit line 860 by measuring the potential=20 difference between the activated bit line 860 and a reference line which = may be=20 an inactive bit line. The operation of Memory device sense amplifiers is = described, for example, in U.S. Pat. Nos. 5,627,785; 5,280,205; and = 5,042,011,=20 all assigned to Micron Technology Inc., and incorporated by reference = herein.=20

FIG. 9 is a block diagram of an electrical system, or = processor-based=20 system, 900 utilizing write once read only memory 912 constructed in = accordance=20 with the present invention. That is, the write once read only memory = (WOROM) 912=20 utilizes the modified DRAM cell as explained and described in detail in=20 connection with FIGS. 2 4. The processor-based system 900 may be a = computer=20 system, a process control system or any other system employing a = processor and=20 associated memory. The system 900 includes a central processing unit = (CPU) 902,=20 e.g., a microprocessor, that communicates with the write once read only = memory=20 912 and an I/O device 908 over a bus 920. It must be noted that the bus = 920 may=20 be a series of buses and bridges commonly used in a processor-based = system, but=20 for convenience purposes only, the bus 920 has been illustrated as a = single bus.=20 A second I/O device 910 is illustrated, but is not necessary to practice = the=20 invention. The processor-based system 900 can also includes read-only = memory=20 (ROM) 914 and may include peripheral devices such as a floppy disk drive = 904 and=20 a compact disk (CD) ROM drive 906 that also communicates with the CPU = 902 over=20 the bus 920 as is well known in the art.

It will be appreciated = by those=20 skilled in the art that additional circuitry and control signals can be=20 provided, and that the memory device 900 has been simplified to help = focus on=20 the invention. At least one of the write once read only memory cell in = WOROM 912=20 includes a programmed MOSFET having a charge trapped in the gate = insulator=20 adjacent to a first source/drain region, or source region, such that the = channel=20 region has a first voltage threshold region (Vt1) and a second voltage = threshold=20 region (Vt2), where Vt2 is greater than Vt1, and Vt2 is adjacent the = source=20 region such that the programmed MOSFET operates at reduced drain source = current.=20

It will be understood that the embodiment shown in FIG. 9 = illustrates an=20 embodiment for electronic system circuitry in which the novel memory = cells of=20 the present invention are used. The illustration of system 900, as shown = in FIG.=20 9, is intended to provide a general understanding of one application for = the=20 structure and circuitry of the present invention, and is not intended to = serve=20 as a complete description of all the elements and features of an = electronic=20 system using the novel memory cell structures. Further, the invention is = equally=20 applicable to any size and type of memory device 900 using the novel = memory=20 cells of the present invention and is not intended to be limited to that = described above. As one of ordinary skill in the art will understand, = such an=20 electronic system can be fabricated in single-package processing units, = or even=20 on a single semiconductor chip, in order to reduce the communication = time=20 between the processor and the memory device.

Applications = containing the=20 novel memory cell of the present invention as described in this = disclosure=20 include electronic systems for use in memory modules, device drivers, = power=20 modules, communication modems, processor modules, and = application-specific=20 modules, and may include multilayer, multichip modules. Such circuitry = can=20 further be a subcomponent of a variety of electronic systems, such as a = clock, a=20 television, a cell phone, a personal computer, an automobile, an = industrial=20 control system, an aircraft, and others.

CONCLUSION =

Utilization=20 of a modification of well established DRAM technology and arrays will = serve to=20 afford an inexpensive memory device. The high density of DRAM array = structures=20 will afford the storage of a large volume of digital data or images at a = very=20 low cost per bit. There are many applications where the data need only = be=20 written once for archival storage. The thicker gate insulators, lower = operating=20 voltages and larger work functions of the nanocrystals acting as = floating gates=20 will insure long retention and archival storage.

It is to be = understood=20 that the above description is intended to be illustrative, and not = restrictive.=20 Many other embodiments will be apparent to those of skill in the art = upon=20 reviewing the above description. The scope of the invention should, = therefore,=20 be determined with reference to the appended claims, along with the full = scope=20 of equivalents to which such claims are entitled.

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