|( 21 of 674 )|
|United States Patent||7,256,451|
|Forbes||August 14, 2007|
A high permittivity gate dielectric formed by low temperature metal oxidation is used in an NROM memory cell. The gate dielectric has a dielectric constant greater than silicon dioxide and is comprised of a nanolaminate structure. The NROM memory cell has a substrate with doped source/drain regions. The high-k gate dielectric is formed above the substrate. A polysilicon control gate is formed on top of the gate dielectric. The gate dielectric may have an oxide-high-k dielectric-oxide composite structure or an oxide-oxide-high-k dielectric composite structure.
|Inventors:||Forbes; Leonard (Corvallis, OR)|
Micron Technology, Inc.
|Filed:||August 9, 2005|
|Current U.S. Class:||257/325 ; 257/310; 257/411; 257/E29.309|
|Current International Class:||H01L 29/792 (20060101)|
|Field of Search:||257/309,324,410,411,E29.309,310,325|
|6599801||July 2003||Chang et al.|
|6838869||January 2005||Rogers et al.|
|2003/0032224||February 2003||Sung et al.|
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