Comparison of phase noise simulation techniques on a BJT LC oscillator
Forbes, L.; Chengwei Zhang; Binglei Zhang; Chandra, Y.
Dept. of Electr. & Comput. Eng., Oregon State Univ.,
Corvallis, OR, USA
IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency
Control, vol.50, no.6, June 2003. p. 716-19.
Abstract:
The phase noise resulting from white and flicker noise in a bipolar junction
transistor (BJT) LC
oscillator is investigated. Large signal transient time domain SPICE simulations
of phase noise
resulting from the random-phase flicker and white noise in a 2 GHz BJT
LC oscillator have been
performed and demonstrated. The simulation results of this new technique
are compared with
Eldo RF and Spectre RF based on linear circuit concepts and experimental
result reported in the
literature. Abstract Number(s): B2003-08-1350F-003; C2003-08-7410D-020
Inspec Heading(s):
bipolar transistor circuits; circuit noise; circuit simulation; flicker
noise; phase noise; time-domain
analysis; transient analysis; UHF oscillators; white noise
Key Phrase Heading(s):
phase noise simulation techniques; BJT LC oscillator; white noise; flicker
noise; bipolar junction
transistor oscillator; large signal SPICE simulations; transient time domain
SPICE simulations;
random-phase flicker; 2 GHz
Classification:
B1350F Solid-state microwave circuits and devices
B1230B Oscillators
B1130B Computer-aided circuit analysis and design
C7410D Electronic engineering computing
Number of References: 9
Copyright Information: Copyright 2003, IEE
1/f noise and clock jitter in digital electronic systems
Forbes, L.; Zhang, C.W.
Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis,
OR, USA
Proceedings of the SPIE - The International Society for Optical
Engineering, vol.5113, 2003. p.168-78.
Abstract:
Timing jitter is a concern in high speed digital integrated circuits, the
presence of timing jitter will
degrade system performance in many high-speed applications. In the first
part of this paper, we
have simulated the timing jitter due to CMOS device noise in a nine stage
CMOS differential ring
oscillator, and a methodology to efficiently simulate timing jitter has
been developed. Simulation
results show the variation of absolute jitter due to flicker noise has
a linear time dependence,
while for white noise it has a square root time dependence, these are consistent
with accepted
theory. Two important parameters cycle jitter, and cycle to cycle jitter
used to describe jitter
performance can be obtained from simulation. Simulation results are also
compared to
experimental results. The methodology developed described in this paper
is also applicable to
other types of clock generators and oscillators such as LC oscillators,
as well as other kinds of
noise sources as power supply and substrate noise. In the second part this
paper, we have
employed this methodology and investigated the timing jitter in silicon
BJT /or SiGe HBT ECL ring
oscillators, and we have shown BJT /or SiGe HBT oscillators have lower
jitter compared to their
CMOS counterparts. As such silicon BJT and/or SiGe HBT ring oscillators
are a potential choice
for low jitter applications. Abstract Number(s): B2004-01-1265Z-001
Inspec Heading(s):
1/f noise; bipolar digital integrated circuits; clocks; CMOS digital integrated
circuits;
emitter-coupled logic; flicker noise; high-speed integrated circuits; integrated
circuit noise;
oscillators; phase noise; timing jitter; white noise
Key Phrase Heading(s):
1/f noise; clock jitter; digital electronic system; timing jitter; high-speed
digital integrated circuit;
cycle jitter; cycle-to-cycle jitter; LC oscillator; power supply noise;
substrate noise; clock generator;
phase noise; CMOS differential ring oscillator; flicker noise; white noise;
SiGe HBT ECL ring
oscillator; silicon BJT ECL ring oscillator; SiGe; Si
Classification:
B1265Z Other digital circuits
B2570D CMOS integrated circuits
B1230B Oscillators
B2570B Bipolar integrated circuits
Number of References:
24
Copyright Information: Copyright 2003, IEE
A theory for Hooge's equation based on temperature fluctuations
Forbes, L.
Dept. of Electr. & Comput. Eng., Oregon State
Univ., Corvallis, OR, USA
Proceedings of the SPIE - The International Society
for Optical Engineering, vol.5113, 2003. p. 43
Abstract:
A description of Hooge's empirical equation is given by temperature fluctuations
and Hooge's
parameter is shown to be simply related to the ratio of the total number
of conduction electrons
and total number of atoms in the sample. Abstract Number(s): B2004-01-2560B-003
Inspec Heading(s):
fluctuations; jitter; phase noise; semiconductor device models; semiconductor
device noise
Key Phrase Heading(s): Hooge's
empirical equation; temperature fluctuations; Hooge's parameter; conduction
electrons
Number of References:
23
Copyright Information:
Copyright 2003, IEE
Experimental verification of the dependence of bipolar transistor flicker
noise on power dissipation
Forbes, L.; Zhang, C.W.; Zhang, B.L.
Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis,
OR, USA
IEEE Transactions on Electron Devices , vol.49, no.5 , Page: 945-7
Publisher: IEEE , May 2002
Language: English
Abstract: Low-frequency 1/f or flicker noise in the frequency range
of Hz
to kHz has been identified and demonstrated
to be described by temperature fluctuations in heat conduction in bipolar
transistors operated at higher power densities.
The noise power spectral density has been shown to depend upon the
increase
in device temperature above the
ambient temperature. (9 References)
Subjects:
1/f noise
bipolar transistors
flicker noise
heat conduction
semiconductor device noise
Experimental
bipolar transistor
flicker noise
power dissipation
low-frequency noise
temperature fluctuations
1/f noise
heat conduction
noise power spectral density
Bipolar transistors
© 2002, IEE
INSPEC
© 2003 Institution of Electrical Engineers. All rights reserved.
Dialog® File Number 2 Accession Number 7257664
SPICE models for flicker noise in n-MOSFETs from subthreshold to strong
inversion
Dingming Xie; Mengzhang Cheng; Forbes, L.
Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis,
OR, USA
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems , vol.19, no.11 , Page:
1293-303
Publisher: IEEE , Nov. 2000
Language: English
Abstract: The two main sources of low-frequency flicker noise are mobility
fluctuations and number fluctuations. Our
experiments on NMOS noise measurements were done from subthreshold
to
saturation region of operation for both
long-channel (5 mu m) and short-channel (as small as 0.6 mu m) NMOS
transistors. The results suggest that for both
types that in the saturation region, the flicker noise is due to the
surface state effect and the noise equations, NLEV=2
and 3, in SPICE, HSPICE, and PSPICE are most appropriate. For short-channel
devices, due to the effects of
velocity saturation and the resulting nonlinear transconductance (g/sub
m/)
variation with gate bias voltage, the
input-referred voltage noise increases as the gate-source voltage increases
instead of staying constant as it does for
long-channel devices. In the subthreshold region, the input-referred
voltage noise decreases drastically as the
gate-source voltage increases for both long-channel and short-channel
NMOS
devices. Simulations have been done
using PSPICE and HSPICE, with noise level (NLEV)=3 and device model
level 3
and BSIM 3.2 and 3.3. The results
from PSPICE version 8.0 level 7 (BSIM 3.3) and SPICE level 3 compare
favorably with the measured noise
phenomena for the short-channel and long-channel NMOS devices,
respectively. (42 References)
Subjects:
1/f noise
circuit simulation
electric noise measurement
flicker noise
MOSFET
semiconductor device noise
SPICE
Theoretical
Experimental
n-MOSFET
SPICE models
flicker noise
mobility fluctuations
drain current noise
NMOS noise measurement
subthreshold region
long-channel
short-channel
NMOS transistors
surface state effect
noise equations
SPICE
HSPICE
PSPICE
velocity saturation
nonlinear transconductance
gate bias voltage
gate-source voltage
short-channel NMOS devices
long-channel NMOS devices
1/f noise
5 mum
0.6 mum
Insulated gate field effect transistors
Semiconductor integrated circuit design, layout, modelling and
testing
Semiconductor device modelling and equivalent circuits
Other topics in statistics
Electric noise and interference measurement
Electronic engineering computing
Other topics in statistics
© 2001, IEE
INSPEC
© 2003 Institution of Electrical Engineers. All rights reserved.
Dialog® File Number 2 Accession Number 6821016
Simulation of phase noise generated by white noise in 1.7 GHz CMOS LC
oscillator
Forbes, L.; Cheng, M.; Zhou, J.
Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis,
OR, USA
Electronics Letters , vol.36, no.23 , Page: 1909-11
Publisher: IEE , 9 Nov. 2000
Language: English
Abstract: The phase noise resulting from upconversion of white noise
in a
CMOS LC oscillator is investigated.
HSPICE simulations of phase noise resulting from the random-phase white
noise in a 1.7 GHz CMOS LC oscillator
have been performed and demonstrate that the phase noise resulting
from the
upconversion of white noise has a
1/f-dependence on the offset frequency and becomes larger as the white
noise increases. The results provide a
confirmation by circuit simulations of Leeson's empirical formula,
and
provide a technique for the design of low noise
oscillators. (7 References)
Subjects:
circuit simulation
CMOS analogue integrated circuits
frequency stability
phase noise
SPICE
UHF integrated circuits
UHF oscillators
voltage-controlled oscillators
white noise
Practical
Theoretical
Experimental
phase noise
white noise
CMOS LC oscillator
upconversion
HSPICE simulations
1/f-dependence
offset frequency
Leeson's empirical formula
1.7 GHz
Oscillators
CMOS integrated circuits
Computer-aided circuit analysis and design
Semiconductor integrated circuit design, layout, modelling and
testing
Nonlinear network analysis and design
Electronic engineering computing
© 2000, IEE
INSPEC
© 2003 Institution of Electrical Engineers. All rights reserved.
Dialog® File Number 2 Accession Number 6779723
Phase noise on a 2-GHz CMOS LC oscillator
Dingming Xie; Forbes, L.
Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems , vol.19, no.7 , Page: 773-8
Publisher: IEEE , July 2000
Language: English
Abstract: This report describes a successful simulation using HSPICE
and
comparison with published data of the
phase noise on a 2-GHz CMOS inductance-capacitance (LC) oscillator
caused
by low-frequency flicker noise (1/f
noise). The flicker noise, which is determined by measurements on NMOSFETs,
is simulated as a sum of sine waves
with random phase by using MATLAB, and is finally introduced into the
LC
oscillator circuit as an HSPICE piecewise
linear waveform. The output of LC oscillator in HSPICE is written as
a
series of points equally spaced in time and then
the spectrum is computed by fast Fourier transform (FFT). The simulation
results show the phase noise of the
voltage-controlled oscillator with different noise coefficient (KF)
values
in the SPICE models, and demonstrate that the
phase noise caused by low-frequency flicker noise has a 1/f/sup 3/
dependence on the offset frequency. The simulated
sideband power spectral density corresponds to the measured values
reported
in the literature. (15 References)
Subjects:
1/f noise
circuit simulation
CMOS analogue integrated circuits
fast Fourier transforms
flicker noise
nonlinear network analysis
piecewise linear techniques
SPICE
UHF integrated circuits
UHF oscillators
voltage-controlled oscillators
Applications
Practical
Experimental
CMOS LC oscillator
HSPICE
low-frequency flicker noise
1/f noise
sine waves
MATLAB
piecewise linear waveform
fast Fourier transform
voltage-controlled oscillator
offset frequency
simulated sideband power spectral density
phase noise
2 GHz
Microwave integrated circuits
CMOS integrated circuits
Integral transforms in numerical analysis
Nonlinear network analysis and design
Computer-aided circuit analysis and design
Oscillators
Semiconductor integrated circuit design, layout, modelling and
testing
Electronic engineering computing
© 2000, IEE
INSPEC
© 2003 Institution of Electrical Engineers. All rights reserved.
Dialog® File Number 2 Accession Number 6672258abstract)