[Databa[Search[Result[RECORD[News][Exit] [Help] [ Database= Inspec | Search=au=("forbes | Results= 81 records | Records= 1, leonard") or 2, au=("forbes 3, l") 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20 ] --------------------------------------------------------------------------- [Email Records] --------------------------------------------------------------------------- Record: 1 COPYRIGHT: Copyright 1996, IEE RECORD NO.: 5450410 INSPEC Abstract No: B9701-2560B-006 AUTHOR: Forbes, L.; Choi, M.S. CORP SOURCE: Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA TITLE: 1/f noise in electron devices due to temperature fluctuations in heat condition SOURCE: 1996. 54th Annual Device Research Conference Digest (Cat. No.96TH8193), p. 202, 46-7 PLACE OF PUBL: USA ISBN: 0780333586 LANGUAGE: English PUBLISHER: IEEE; New York, NY, USA SPONSOR ORG: IEEE Electron Devices Soc CONF TITLE: 1996 54th Annual Device Research Conference Digest CONF LOCATION: Santa Barbara, CA, USA; 24-26 June 1996 YEAR: 1996 TREATMENT: P Practical; T Theoretical or Mathematical ABSTRACT: It is shown that power dissipation in electron devices will result in temperature fluctuations which are frequency dependent and consequently l/f noise. As an example, application of this theory to diode and laser diodes with significant power dissipation is considered. The latter are of interest since it has been previously reported that the spectral intensity of the l/f noise varies linearly with the applied DC current and not as is usual in most electron devices as the square of the DC voltage or current as described by Hooge's empirical relationship. We will show results on a simple diode where the mean square noise voltage at low frequency varies linearly with the applied DC current. The results have also been applied to describe measurements on resistive filaments in vacuum such as in light bulbs or vacuum tube devices where there is significant power dissipation and heat conduction. Temperature fluctuations in heat conduction result in l/f fluctuations in resistance of the filament. These results might well do much to clarify the long lack of understanding of l/f noise in vacuum tube devices (3 Refs.) DESCRIPTORS: 1/f noise; equivalent circuits; semiconductor device models; semiconductor device noise; semiconductor diodes; semiconductor lasers; vacuum tubes IDENTIFIERS: 1/f noise; electron devices; temperature fluctuations; heat condition; power dissipation; laser diodes; spectral intensity; applied DC current; semiconductor diode; mean square noise voltage; resistive filaments; vacuum tube devices CLASS CODES: B2560B (Semiconductor device modelling and equivalent circuits); B2340 (Vacuum tubes); B2560H (Junction and barrier diodes); B4320J (Semiconductor lasers) --------------------------------------------------------------------------- Record: 2 COPYRIGHT: Copyright 1996, IEE RECORD NO.: 5322338 INSPEC Abstract No: B9608-2560S-020 AUTHOR: Yan, K.T.; Forbes, L. CORP SOURCE: Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA TITLE: A model for the 1/f noise corner frequency of FETs on semi- insulating substrates based on bulk phenomena: Theory and experiments SOURCE: Solid-State Electronics, vol.39, no.6, p. 857-61 ISSN: 0038-1101 CODEN: SSELA5 PLACE OF PUBL: UK LANGUAGE: English PUBLISHER: Elsevier YEAR: June 1996 COPYRIGHT NO: 0038-1101/96/$15.00+0.00 TREATMENT: T Theoretical or Mathematical; X Experimental ABSTRACT: We have developed a formula for the 1/f noise corner frequency for GaAs MESFETs. The formula is based on a new theory where the 1/f noise is a bulk phenomena with localized high frequency variations and long range low frequency fluctuations in the substrate with the lowest frequency being constrained only by the thickness of the material. The model is based on employing a distributed equivalent circuit technique in evaluating the semi- insulating substrate. Preliminary results demonstrate a close consistency between modeled and measured data (20 Refs.) DESCRIPTORS: 1/f noise; equivalent circuits; gallium arsenide; III-V semiconductors; Schottky gate field effect transistors; semiconductor device models; semiconductor device noise IDENTIFIERS: 1/f noise corner frequency; semiinsulating substrates; bulk phenomena; GaAs MESFET; frequency fluctuations; distributed equivalent circuit technique; GaAs CLASS CODES: B2560S (Other field effect devices); B2560B (Semiconductor device modelling and equivalent circuits) --------------------------------------------------------------------------- Record: 3 COPYRIGHT: Copyright 1996, IEE RECORD NO.: 5315974 INSPEC Abstract No: B9608-2560S-017 AUTHOR: Yan, K.T.; Forbes, L. EDITOR: Ong, S.H.; Radhakrishnan, M.K. CORP SOURCE: Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA TITLE: Design for and the control of the channel and 1/f noise in GaAs MESFET's SOURCE: Proceedings of the 1995 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.95TH8113), p. 233, 164-8 PLACE OF PUBL: USA ISBN: 0780327977 LANGUAGE: English PUBLISHER: IEEE; New York, NY, USA SPONSOR ORG: IEEE Electron Devices Soc.; Natl. Univ. Singapore; Inst. Microelectron., Singapore; Magn. Technol. Centre, Singapore CONF TITLE: Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits CONF LOCATION: Singapore; 27 Nov.-1 Dec. 1995 YEAR: 1995 COPYRIGHT NO: 0 7803 2797 7/95/$4.00 TREATMENT: T Theoretical or Mathematical ABSTRACT: A model is given for the channel noise coefficient of FETs operating in the saturation region. Some approximations are made for hot electron effects which can be incorporated into the derivation and accounted for by a simple numerical technique. These are then compared to experimental results. We have also developed a formula for the 1/f noise corner frequency for GaAs MESFETs. The formula is based on a new theory where the 1/f noise is a bulk phenomena with localized high frequency variations and long range low frequency fluctuations of carrier concentrations in the substrate with the lowest frequency constrained only by the thickness of the material. Comprehensive and new models with matching experimental data for both channel noise and 1/f noise of the GaAs MESFETs are presented. These can provide both design and testing guidelines for devices in GaAs integrated circuits which are required to meet noise and reliability specifications (9 Refs.) DESCRIPTORS: 1/f noise; carrier density; equivalent circuits; gallium arsenide; hot carriers; III-V semiconductors; Schottky gate field effect transistors; semiconductor device models; semiconductor device noise; semiconductor device reliability IDENTIFIERS: channel noise control; 1/f noise control; GaAs MESFET; models; channel noise coefficient; saturation region; hot electron effects; 1/f noise corner frequency; carrier concentrations; reliability; GaAs CLASS CODES: B2560S (Other field effect devices); B2560B (Semiconductor device modelling and equivalent circuits); B0170N (Reliability) --------------------------------------------------------------------------- Record: 4 COPYRIGHT: Copyright 1996, IEE RECORD NO.: 5315970 INSPEC Abstract No: B9608-1280-006 AUTHOR: Forbes, L.; Lim, W.T.; Yan, K.T. EDITOR: Ong, S.H.; Radhakrishnan, M.K. CORP SOURCE: Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA TITLE: Guard ring diodes for suppression of substrate noise and improved reliability in mixed-mode CMOS circuits SOURCE: Proceedings of the 1995 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.95TH8113), p. 233, 145-8 PLACE OF PUBL: USA ISBN: 0780327977 LANGUAGE: English PUBLISHER: IEEE; New York, NY, USA SPONSOR ORG: IEEE Electron Devices Soc.; Natl. Univ. Singapore; Inst. Microelectron., Singapore; Magn. Technol. Centre, Singapore CONF TITLE: Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits CONF LOCATION: Singapore; 27 Nov.-1 Dec. 1995 YEAR: 1995 COPYRIGHT NO: 0 7803 2797 7/95/$4.00 TREATMENT: P Practical; X Experimental ABSTRACT: Forward biased n/sup +/ guard ring diodes are used to generate a relatively large on-chip capacitance. This variable capacitance is resonated with the normal substrate lead inductance to form a very low impedance path to ground. In this manner, substrate noise in mixed signal CMOS integrated circuits can be suppressed resulting in less noise and improved reliability in analog portions of the mixed mode circuits (7 Refs.) DESCRIPTORS: capacitance; CMOS integrated circuits; integrated circuit noise; integrated circuit reliability; interference suppression; mixed analogue-digital integrated circuits; semiconductor diodes IDENTIFIERS: guard ring diodes; substrate noise suppression; reliability; mixed-mode CMOS circuits; forward biased n/sup +/ diodes; onchip capacitance; variable capacitance; substrate lead inductance; CMOS integrated circuits CLASS CODES: B1280 (Mixed analogue-digital circuits); B2570D (CMOS integrated circuits); B0170N (Reliability) --------------------------------------------------------------------------- Record: 5 COPYRIGHT: Copyright 1996, IEE RECORD NO.: 5262625 INSPEC Abstract No: B9606-2560S-037 AUTHOR: Yan, K.T.; Forbes, L. CORP SOURCE: Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA TITLE: 1/f bulk phenomena noise theory for GaAs MESFETs SOURCE: 1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. Asia-Pacific Microelectronics 2000. Proceedings (Cat. No.95CH35787), p. xvi+499, 111-14 PLACE OF PUBL: USA ISBN: 0780326245 LANGUAGE: English PUBLISHER: IEEE; New York, NY, USA SPONSOR ORG: IEEE Hong Kong Sect.; IEEE Asia-Pacific Region; IEEE Solid State Council; IEEE Electron. Devices Soc.; IEE Hong Kong Centre; Hong Kong Inst. Eng CONF TITLE: 1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. Asia-Pacific Microelectronics 2000. Proceedings CONF LOCATION: Hong Kong; 6-10 Nov. 1995 YEAR: 1995 COPYRIGHT NO: 0 7803 2624 5/95/$4.00 TREATMENT: T Theoretical or Mathematical; X Experimental ABSTRACT: A 1/f noise model based on the distributed equivalent circuit technique for evaluating the semi-insulating substrate is proposed. Our model shows that the 1/f noise is a bulk phenomena with localized high frequency variations and long range low frequency fluctuations with the lowest frequency being constrained by the thickness of the material (6 Refs.) DESCRIPTORS: 1/f noise; equivalent circuits; gallium arsenide; III-V semiconductors; Schottky gate field effect transistors; semiconductor device models; semiconductor device noise IDENTIFIERS: 1/f bulk phenomena noise theory; MESFETs; 1/f noise model; distributed equivalent circuit technique; semi-insulating substrate; localized HF variations; long range LF fluctuations; GaAs CLASS CODES: B2560S (Other field effect devices); B2560B (Semiconductor device modelling and equivalent circuits) --------------------------------------------------------------------------- Record: 6 COPYRIGHT: Copyright 1996, IEE RECORD NO.: 5251676 INSPEC Abstract No: B9606-2560Z-002 AUTHOR: Forbes, L.; Mun Seork Choi; Yan, K.T. CORP SOURCE: Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA TITLE: 1/f noise of GaAs resistors on semi-insulating substrates SOURCE: IEEE Transactions on Electron Devices, vol.43, no.4, p. 622- 7 ISSN: 0018-9383 CODEN: IETDAI PLACE OF PUBL: USA LANGUAGE: English PUBLISHER: IEEE YEAR: April 1996 COPYRIGHT NO: 0018-9383/96/$05.00 TREATMENT: T Theoretical or Mathematical ABSTRACT: A new theory is used to analyze the 1/f noise of GaAs resistors on semi-insulating substrates. It is demonstrated that this model can explain previously published results at moderately high frequencies for, in this example, resistive filaments on semi-insulating GaAs substrates. The model is based on a distributed equivalent circuit representation of the substrate, and shows that 1/f noise is a bulk phenomenon associated with the high resistivity substrates. The 1/f noise is not associated with number or mobility fluctuations in the channel, nor surface effects. One consequence of the theory is that in this particular instance Hooges parameter is in reality no parameter, but is given by a simple formula which has a simple physical interpretation as the ratio of two charges: the thermal charge developed across the substrate capacitance and the charge associated with ionized donors in the resistor channel (27 Refs.) DESCRIPTORS: 1/f noise; equivalent circuits; gallium arsenide; III-V semiconductors; resistors; Schottky gate field effect transistors; semiconductor device models; semiconductor device noise; substrates IDENTIFIERS: 1/f noise; GaAs resistors; semi-insulating substrates; model; resistive filaments; distributed equivalent circuit representation; Hooge parameter; thermal charge; ionized donor charge; substrate capacitance; MESFET; GaAs CLASS CODES: B2560Z (Other semiconductor devices); B2560B (Semiconductor device modelling and equivalent circuits); B2560S (Other field effect devices); B2120 (Resistors) --------------------------------------------------------------------------- Record: 7 COPYRIGHT: Copyright 1995, IEE RECORD NO.: 5068595 INSPEC Abstract No: A9521-7270-002; B9511-2520-002 AUTHOR: Forbes, L. CORP SOURCE: Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA TITLE: On the theory of 1/f noise of semi-insulating materials SOURCE: IEEE Transactions on Electron Devices, vol.42, no.10, p. 1866-8 ISSN: 0018-9383 CODEN: IETDAI PLACE OF PUBL: USA LANGUAGE: English YEAR: Oct. 1995 COPYRIGHT NO: 0018-9383/95/$04.00 TREATMENT: T Theoretical or Mathematical ABSTRACT: The 1/f noise phenomena associated with devices involving semi-insulating materials, for instance GaAs MESFET's on semi-insulating GaAs, has long been a perplexing problem. In this particular case the 1/f noise corner frequency can be up to 100 MHz before the mean square noise current at the drain is dominated by the Nyquist noise associated with the channel conductance. No reasonable explanation has ever been given, although there are many different theories. 1/f noise is a common phenomena in nature and other devices involving semi-insulating materials. We propose here that this 1/f noise is a bulk phenomena associated with localized high frequency variations and long range low frequency fluctuations, the lowest frequency being limited only by the volume of the material. Specifically the proposal here is that injection of a current I into a semi-insulating material will result in a mean square noise voltage at the point of injection given by v/sub n//sup 2/=2(kT/q)q Delta fR( omega /sub c// omega ) Volts/sup 2/ where omega /sub c/=1/t/sub t/, for the radian frequencies, omega , larger than omega /sub c/ which is the reciprocal of the transit time of the carriers. For a long sample and long transit times then this 1/f noise voltage due to current injection will be larger than the Nyquist mean square noise of the sample alone as long as the DC voltage developed across the semi-insulating sample exceeds ((2kT/q)l/sup 2/( omega / mu ))/sup 1/2/. This theory then gives the 1/f or 1/ omega frequency dependence. The dc current I might be injected for instance by the substrate current in a GaAs MESFET being injected into the semi-insulating substrate, or gate current in an IGET being injected into the gate insulator (11 Refs.) DESCRIPTORS: 1/f noise; semiconductor materials IDENTIFIERS: 1/f noise; semi-insulating materials; GaAs MESFETs; corner frequency; Nyquist noise; channel conductance; current injection CLASS CODES: A7270 (Noise processes and phenomena in electronic transport)B2520 (Semiconductor theory, materials and properties) --------------------------------------------------------------------------- Record: 8 COPYRIGHT: Copyright 1995, IEE RECORD NO.: 4958787 INSPEC Abstract No: B9507-1280-002 AUTHOR: Forbes, L.; Ficq, B.; Savage, S. CORP SOURCE: Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA TITLE: Resonant forward-biased guard-ring diodes for suppression of substrate noise in mixed-mode CMOS circuits SOURCE: Electronics Letters, vol.31, no.9, p. 720-1 ISSN: 0013-5194 CODEN: ELLEAK PLACE OF PUBL: UK LANGUAGE: English YEAR: 27 April 1995 COPYRIGHT NO: 0013-5194/95/$10.00 TREATMENT: P Practical; X Experimental ABSTRACT: Substrate noise is a serious concern and a limitation in mixed-mode, analogue-digital, CMOS integrated circuits. The use of forward-biased n/sup +/p/sup upsilon /ard-ring diodes which resonate with substrate lead inductance is demonstrated by simulations to be effective in reducing this substrate noise by an order of magnitude (6 Refs.) DESCRIPTORS: CMOS integrated circuits; integrated circuit noise; interference suppression; isolation technology; mixed analogue-digital integrated circuits IDENTIFIERS: resonant forward-biased diodes; guard-ring diodes; substrate noise suppression; mixed-mode CMOS ICs; analogue-digital integrated circuits; substrate lead inductance CLASS CODES: B1280 (Mixed analogue-digital circuits); B2570D (CMOS integrated circuits) --------------------------------------------------------------------------- Record: 9 COPYRIGHT: Copyright 1995, IEE RECORD NO.: 4867586 INSPEC Abstract No: B9503-2560R-035 AUTHOR: Nam Hwang; Forbes, L. CORP SOURCE: Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA TITLE: Hot-carrier induced series resistance enhancement model (HISREM) of nMOSFET's for circuit simulations and reliability projections SOURCE: Microelectronics and Reliability, vol.35, no.2, p. 225-40 ISSN: 0026-2714 CODEN: MCRLAS PLACE OF PUBL: UK LANGUAGE: English YEAR: Feb. 1995 COPYRIGHT NO: 0026-2714/95/$9.50+.00 TREATMENT: T Theoretical or Mathematical ABSTRACT: This paper proposes a physically realizable reliability model of nMOSFET's that is applicable for reliability projections in IC design. We have devised a hot-carrier induced series (drain) resistance enhancement model (HISREM) which is based on the increase of the interface trapped charge ( Delta Nit) near the drain region and is physically realizable in circuit simulations of the hot-carrier induced degradation under operating conditions. The proposed HISREM requires only one parameter ( Delta Nit) for reliability projections in IC design without extraction of a set of stressed parameter files. The proposed HISREM shows a good agreement between the simulation results from SPICE and experiment data of the hot-carrier induced degradation of device characteristics. The HISREM has been demonstrated by employing a NMOS inverter and a conventional CMOS operational amplifier. The HISREM is shown to be much simpler and more efficient for reliability projections in both digital and analog IC design rather than the commercial reliability simulator with parameter degradation models which require extraction of a set of stressed parameter files (i.e., Vto, gamma , mu /sub 0/, theta , V/sub max/, kappa ) (23 Refs.) DESCRIPTORS: hot carriers; integrated circuit reliability; MOS integrated circuits; MOSFET; semiconductor device models; SPICE IDENTIFIERS: hot-carrier induced series resistance enhancement model; SPICE; HISREM; nMOSFETs; circuit simulations; reliability; interface trapped charge; hot-carrier induced degradation; NMOS inverter; CMOS operational amplifier; analog IC design; digital IC design CLASS CODES: B2560R (Insulated gate field effect transistors); B2560B (Semiconductor device modelling and equivalent circuits); B0170N (Reliability); B2570F (Other MOS integrated circuits); B1130B (Computer-aided circuit analysis and design) --------------------------------------------------------------------------- Record: 10 RECORD NO.: 4786494 INSPEC Abstract No: B9411-1220-014 AUTHOR: Kurachi, I.; Yan, K.T.; Forbes, L. CORP SOURCE: Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA TITLE: Reliability considerations of hot-carrier induced degradation in analogue nMOSFET amplifier SOURCE: Electronics Letters, vol.30, no.19, p. 1568-70 ISSN: 0013-5194 CODEN: ELLEAK PLACE OF PUBL: UK LANGUAGE: English YEAR: 15 Sept. 1994 COPYRIGHT NO: 0013-5194/94/$7.50+0.00 TREATMENT: P Practical; T Theoretical or Mathematical ABSTRACT: A successful implementation of substrate current and gain degradation models for an nMOSFET amplifier is demonstrated. The substrate current has to be taken into consideration in order to predict the drain conductance degradation. It is shown that the V/sub gs/ bias point for the nMOSFET amplifier is very limited when reliability is taken into consideration (5 Refs.) DESCRIPTORS: amplifiers; circuit reliability; CMOS integrated circuits; hot carriers; linear integrated circuits IDENTIFIERS: hot-carrier induced degradation; analogue nMOSFET amplifier; substrate current; gain degradation models; drain conductance degradation; bias point; reliability; CMOS CLASS CODES: B1220 (Amplifiers); B2570D (CMOS integrated circuits); B0170N (Reliability) --------------------------------------------------------------------------- Record: 11 RECORD NO.: 4727775 INSPEC Abstract No: B9409-2560R-056 AUTHOR: Kurachi, I.; Nam Hwang; Forbes, L. CORP SOURCE: Process Technol. Center, OKI Electr. Ind. Co. Ltd., Tokyo, Japan TITLE: Physical model of drain conductance, g/sub d/, degradation of NMOSFET's due to interface state generation by hot carrier injection SOURCE: IEEE Transactions on Electron Devices, vol.41, no.6, p. 964- 9 ISSN: 0018-9383 CODEN: IETDAI PLACE OF PUBL: USA LANGUAGE: English YEAR: June 1994 COPYRIGHT NO: 0018-9383/94/$04.00 TREATMENT: T Theoretical or Mathematical; X Experimental ABSTRACT: Degradation of analog device parameters such as drain conductance, g/sub d/, due to hot carrier injection has been modeled for NMOSFET's. In this modeling, mobility reduction caused by interface state generation by hot carrier injection and the gradual channel approximation were employed. It has been found that g/sub d/ degradation can be calculated from linear region transconductance, g/sub m/, degradation which is usually monitored for hot carrier degradation of MOSFET's. The values of g/sub d/ degradation calculated from g/sub m/ degradation fit well to the measured values of g/sub d/ degradation The dependence of the g/sub d/ degradation lifetime on L/sub eff/ has been also studied, this model also provides an explanation of the dependence on L/sub eff/. The model is then useful for lifetime predictions of analog circuits in which g/sub d/ degradation is usually more important than g/sub m/ degradation (15 Refs.) DESCRIPTORS: carrier lifetime; carrier mobility; hot carriers; insulated gate field effect transistors; interface electron states; semiconductor device models IDENTIFIERS: physical model; drain conductance degradation; NMOSFET; interface state generation; hot carrier injection; analog device parameters; mobility reduction; gradual channel approximation; degradation lifetime; n-channel MOSFET CLASS CODES: B2560R (Insulated gate field effect transistors); B2560B (Modelling and equivalent circuits) --------------------------------------------------------------------------- Record: 12 RECORD NO.: 4447676 INSPEC Abstract No: B9309-2560R-004 AUTHOR: Hwang, N.; Or, B.S.S.; Forbes, L. CORP SOURCE: Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA TITLE: Tunneling and thermal emission of electrons from a distribution of deep traps in SiO/sub 2/ (nMOSFET) SOURCE: IEEE Transactions on Electron Devices, vol.40, no.6, p. 1100- 3 ISSN: 0018-9383 CODEN: IETDAI PLACE OF PUBL: USA LANGUAGE: English YEAR: June 1993 COPYRIGHT NO: 0018-9383/93/$03.00 TREATMENT: T Theoretical or Mathematical; X Experimental ABSTRACT: Both field-induced, or tunneling, and thermal emission of electrons from deep traps in the gate oxides on n-channel LDD CMOS devices have been observed and characterized. Experimental results show that the deep trapping effects at room temperature are similar to the shallow-level trapping effects observed by others below room temperature. In this case, however, the time constants involved are very long. This model and physical mechanisms can explain the apparent saturation observed under AC stress conditions, and also the differences observed between AC use conditions and DC stress (10 Refs.) DESCRIPTORS: deep levels; hot carriers; insulated gate field effect transistors; semiconductor device models; tunnelling IDENTIFIERS: thermal electron emission; field induced electron emission; hot electrons; deep traps; tunneling; gate oxides; n-channel LDD CMOS devices; time constants; model; physical mechanisms; apparent saturation; AC stress conditions; DC stress; Si-SiO/sub 2/ CLASS CODES: B2560R (Insulated gate field effect transistors); B2560B (Modelling and equivalent circuits) --------------------------------------------------------------------------- Record: 13 RECORD NO.: 4404268 INSPEC Abstract No: B9306-2560R-090 AUTHOR: Ge, D.Y.; Hwang, N.; Forbes, L. CORP SOURCE: Oregon State Univ., Corvallis, OR, USA TITLE: Composite n-MOSFET for submicrometre circuits SOURCE: Electronics Letters, vol.29, no.7, p. 623-5 ISSN: 0013-5194 CODEN: ELLEAK PLACE OF PUBL: UK LANGUAGE: English YEAR: 1 April 1993 COPYRIGHT NO: 0013-5194/93/$7.50+0.00 TREATMENT: N New Development; P Practical; X Experimental ABSTRACT: Proposes a new composite n-MOS device to replace conventional n-channel devices in submicrometre amplifier circuits whenever a large drain-source voltage is encountered. The composite device improves the lifetime of a simple amplifier by eight orders of magnitude. Increasing the device channel length to reduce the effects of hot electron degradation has also been investigated as an alternative in contrast to the composite device, but is demonstrated to be an inferior design choice (5 Refs.) DESCRIPTORS: amplifiers; hot carriers; insulated gate field effect transistors; MOS integrated circuits; reliability IDENTIFIERS: composite n-MOSFET; lifetime increase; device reliability; hot-electron degradation reduction; submicrometre circuits; composite n-MOS device; submicrometre amplifier circuits; large drain-source voltage; device channel length CLASS CODES: B2560R (Insulated gate field effect transistors); B1220 (Amplifiers); B0170N (Reliability); B2570F (Other MOS integrated circuits) --------------------------------------------------------------------------- Record: 14 RECORD NO.: 4272369 INSPEC Abstract No: B9212-2530F-012 AUTHOR: Imthurn, G.P.; Garcia, G.A.; Walker, H.W.; Forbes, L. CORP SOURCE: Naval Command, Control & Ocean Surveillance Center, RDT&E Div., San Diego, CA, USA TITLE: Bonded silicon-on-sapphire wafers and devices SOURCE: Journal of Applied Physics, vol.72, no.6, p. 2526-7 ISSN: 0021-8979 CODEN: JAPIAU PLACE OF PUBL: USA LANGUAGE: English YEAR: 15 Sept. 1992 COPYRIGHT NO: 0021-8979/92/182526-02$04.00 TREATMENT: X Experimental ABSTRACT: Silicon-on-sapphire (SOS) has been prepared by direct wafer bonding. The silicon layer was thinned to about 10 mu m by mechanical grinding and chemical etching, P-N junction diodes were fabricated in the bonded SOS and compared with epitaxially grown SOS. The reverse bias leakage current was almost 15*less in the bonded SOS. A generation lifetime of 10 mu s can be estimated from the junction leakage. The effects of processing temperatures on the bonded SOS were also studied (6 Refs.) DESCRIPTORS: adhesion; carrier lifetime; leakage currents; semiconductor diodes; semiconductor technology; semiconductor-insulator boundaries IDENTIFIERS: semiconductor; thinning; silicon-on-sapphire; devices; direct wafer bonding; mechanical grinding; chemical etching; P-N junction diodes; SOS; leakage current; generation lifetime; Si-Al/sub 2/O/sub 3/ CLASS CODES: B2530F (Metal-insulator-semiconductor structures); B2550 (Semiconductor device technology); B2560H (Junction and barrier diodes) --------------------------------------------------------------------------- Record: 15 RECORD NO.: 4155312 INSPEC Abstract No: B9206-2560R-075 AUTHOR: Lee, M.; Or, B.S.S.; Hwang, N.; Forbes, L.; Haddad, H.; Richling, W. CORP SOURCE: Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA TITLE: Thermal self-limiting effects in the long-term AC stress on n-channel LDD MOSFETs SOURCE: Proceedings. Ninth Biennial University/Government/Industry Microelectronics Symposium (Cat. No.91CH3027-0), p. 262, 93- 7 PLACE OF PUBL: USA ISBN: 0780301099 LANGUAGE: English PUBLISHER: IEEE; New York, NY, USA SPONSOR ORG: IEEE; SEMATECH; Florida Inst. Technol CONF LOCATION: Melbourne, FL, USA; 12-14 June 1991 YEAR: 1991 COPYRIGHT NO: 0 7803 0109 9/91/0000-0093$01.00 TREATMENT: P Practical; T Theoretical or Mathematical; X Experimental ABSTRACT: A model of lightly doped drain n-MOSFET degradation in drain current under long-term AC use conditions which includes a self-limiting effect in the hot-electron induced device degradation is proposed for lifetime projections. Experimental results on LDD n-MOSFETs (W=50 mu m) are presented which show the maximum drain current degradation as a function of the average substrate current under the various AC stress and use conditions (f=0.4 MHz, 1 MHz, 2 MHz, and 4 MHz) for different drawn gate lengths. The maximum drain current degradations were 0.3% mu A, 0.2%/ mu A, and 0.15%/ mu A of the substrate current for drawn gate lengths of 0.8 mu m, 1.0 mu m, and 1.5 mu m, respectively, at an ambient temperature of 25 degrees C. The proposed model also includes and predicts the strong temperature dependence (6 Refs.) DESCRIPTORS: carrier lifetime; insulated gate field effect transistors; semiconductor device models IDENTIFIERS: long-term AC stress; n-channel LDD MOSFETs; lightly doped drain; drain current; self-limiting effect; lifetime projections; average substrate current; drawn gate lengths; ambient temperature; 0.2 to 4 MHz; 25 degC CLASS CODES: B2560R (Insulated gate field effect transistors); B2560B (Modelling and equivalent circuits) --------------------------------------------------------------------------- Record: 16 RECORD NO.: 4093329 INSPEC Abstract No: B9204-2560R-024 AUTHOR: Or, B.S.S.; Forbes, L.; Haddad, H.; Richling, W. CORP SOURCE: Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA TITLE: Annealing effects of carbon in n-channel LDD MOSFETs SOURCE: IEEE Electron Device Letters, vol.12, no.11, p. 596-8 ISSN: 0741-3106 CODEN: EDLEDZ PLACE OF PUBL: USA LANGUAGE: English YEAR: Nov. 1991 COPYRIGHT NO: 0741-3106/91/1100-0596$01.00 TREATMENT: X Experimental ABSTRACT: The degradation pattern of lightly doped drain (LDD) structure MOSFETs with carbon doping under various steps has been studied. For a carbon-doped LDD device with first- and second-level metal and passivation layer but without any final anneal, the results show that a significant reduction in the shifts of the threshold voltage of MOSFETs with time can be achieved. The authors demonstrate that threshold voltage degradation has been reduced for carbon-doped devices and that a final anneal does not improve the hot- electron degradation of these devices. These results imply the existence of neutral electron traps in the gate oxides of MOSFETs (9 Refs.) DESCRIPTORS: carbon; elemental semiconductors; hot carriers; insulated gate field effect transistors; semiconductor doping; silicon IDENTIFIERS: threshold voltage shifts reduction; annealing effects; semiconductors; n-channel LDD MOSFETs; degradation pattern; second-level metal; passivation layer; threshold voltage degradation; hot-electron degradation; neutral electron traps; gate oxides; Si:C; Si-SiO/sub 2/; SiO/sub 2/ CLASS CODES: B2560R (Insulated gate field effect transistors); B2550B (Semiconductor doping) --------------------------------------------------------------------------- Record: 17 RECORD NO.: 4093063 INSPEC Abstract No: B9204-2560R-017 AUTHOR: Or, S.S.B.; Forbes, L.; Haddad, H. CORP SOURCE: Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA TITLE: Thermal re-emission of trapped hot electrons in NMOS transistors SOURCE: IEEE Trans. Electron Devices (USA), IEEE Transactions on Electron Devices, vol.38, no.12, p. 2712 ISSN: 0018-9383 CODEN: IETDAI PLACE OF PUBL: USA LANGUAGE: English SPONSOR ORG: IEEE CONF TITLE: 49th Annual Device Research Conference (papers in summary form only received) CONF LOCATION: Boulder, CO, USA; 17-19 June 1991 YEAR: Dec. 1991 COPYRIGHT NO: 0018-9383/91/1200-2712$01.00 TREATMENT: T Theoretical or Mathematical ABSTRACT: Summary form only given. A simple model of injection and thermal re-emission is shown to be adequate for predicting the hot-electron-injection-induced degradation on submicrometer NMOS technology under AC stress. Hot-carrier stressing has been carried out on LDD NMOS transistors under various AC use conditions. An example of the results shows that a 14% degradation in drain current is fully recovered after 3500 min at 70 degrees C. From the Arrhenius plot of the recovery phase, a 1.5-eV activation energy of the trapped electrons in SiO/sub 2/ has been extracted (2 Refs.) DESCRIPTORS: electron traps; hot carriers; insulated gate field effect transistors; MOS integrated circuits; semiconductor device models IDENTIFIERS: submicron LDD transistors; thermal reemission; NMOSFET; carrier injection; trapped hot electrons; NMOS transistors; model; thermal re-emission; hot-electron-injection-induced degradation; submicrometer NMOS technology; AC stress; SiO/sub 2/ CLASS CODES: B2560R (Insulated gate field effect transistors); B2560B (Modelling and equivalent circuits); B2570F (Other MOS integrated circuits) --------------------------------------------------------------------------- Record: 18 RECORD NO.: 3876379 INSPEC Abstract No: B91030177 AUTHOR: Lee, M.; Forbes, L.; Hallen, T. CORP SOURCE: Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA TITLE: Design of a GaAs operational amplifier using a self- backgating MESFET model including deep-level trap effects SOURCE: 1990 IEEE International Symposium on Circuits and Systems (Cat. No.90CH2868-8), p. 4 vol. xxxix+3289, 2287-90 vol.3 PLACE OF PUBL: USA LANGUAGE: English PUBLISHER: IEEE; New York, NY, USA SPONSOR ORG: IEEE CONF LOCATION: New Orleans, LA, USA; 1-3 May 1990 YEAR: 1990 COPYRIGHT NO: CH2868-8/90/0000-2287$01.00 TREATMENT: T Theoretical or Mathematical ABSTRACT: A GaAs op amp has been designed using a self-backgating MESFET model which can simulate low-frequency anomalies and also has been fabricated by a 0.5- mu m conventional MESFET technology. This model has been incorporated into PSPICE and includes an analytical DC and capacitance model with an RC network providing device symmetry. The op amp has three inverting stages, series-shunt feedback, and internal compensation with forward blocking to achieve unique stability. Measured data corresponds to simulations by the model. The authors have obtained a 35-dB open-loop gain in the high-frequency regime, 4-GHz gain-bandwidth product, an output voltage-swing range of -3.7 V to 3.4 V, and a total power dissipation of 0.46 W. The low-frequency anomalies of the GaAs amplifier are more accurately predicted using this model than with any other previous model (6 Refs.) DESCRIPTORS: circuit CAD; deep levels; electron traps; equivalent circuits; feedback; gallium arsenide; hole traps; III-V semiconductors; linear integrated circuits; operational amplifiers; Schottky gate field effect transistors; semiconductor device models IDENTIFIERS: DC model; operational amplifier; self-backgating MESFET model; deep-level trap effects; op amp; PSPICE; capacitance model; RC network; device symmetry; inverting stages; series- shunt feedback; internal compensation; forward blocking; stability; 0.5 micron; 35 dB; -3.7 to 3.4 V; 0.46 W; GaAs CLASS CODES: B1220 (Amplifiers); B2560B (Modelling and equivalent circuits); B2560S (Other field effect devices); B1130B (Computer-aided circuit analysis and design); B2570 (Semiconductor integrated circuits) --------------------------------------------------------------------------- Record: 19 RECORD NO.: 3809785 INSPEC Abstract No: B91009234 AUTHOR: Haddad, H.; Forbes, L.; Burke, P.; Richling, W. CORP SOURCE: Hewlett-Packard, Corvallis, OR, USA TITLE: Carbon doping effects on hot electron trapping SOURCE: 28th Annual Proceedings. Reliability Physics 1990 (Cat. No.90CH2787-0), p. vi+322, 288-9 PLACE OF PUBL: USA LANGUAGE: English PUBLISHER: IEEE; New York, NY, USA SPONSOR ORG: IEEE CONF LOCATION: New Orleans, LA, USA; 27-29 March 1990 YEAR: 1990 COPYRIGHT NO: CH2787-0/90/0000-0288$01.00 TREATMENT: X Experimental ABSTRACT: The injection of hot electrons in submicrometer MOS devices constitutes a serious limitation on the application and reliability of these devices. It is shown that carbon doping can significantly reduce or delay this ageing process and the shifts of threshold voltages of MOS transistors with time. Carbon doping has been achieved by both using carbon- doped substrates and by ion implantation of carbon (5 Refs.) DESCRIPTORS: ageing; carbon; elemental semiconductors; hot carriers; insulated gate field effect transistors; reliability; semiconductor doping; silicon IDENTIFIERS: hot electron trapping; injection of hot electrons; submicrometer MOS devices; limitation; reliability; ageing process; shifts of threshold voltages; MOS transistors; ion implantation; Si:C CLASS CODES: B2550B (Semiconductor doping); B2560R (Insulated gate field effect transistors); B0170N (Reliability) --------------------------------------------------------------------------- Record: 20 RECORD NO.: 3803726 INSPEC Abstract No: B91008531 AUTHOR: Lee, M.; Forbes, L. CORP SOURCE: Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA TITLE: A self-backgating GaAs MESFET model for low-frequency anomalies SOURCE: IEEE Transactions on Electron Devices, vol.37, no.10, p. 2148-57 ISSN: 0018-9383 CODEN: IETDAI PLACE OF PUBL: USA LANGUAGE: English YEAR: Oct. 1990 COPYRIGHT NO: 0018-9383/90/1000-2148$01.00 TREATMENT: T Theoretical or Mathematical; X Experimental ABSTRACT: A self-backgating GaAs MESFET model which can simulate low- frequency anomalies has been developed by including deep- level trap effects. These cause transconductance reduction due to electron emission from EL2 in the depletion width change at the edge of the Schottky gate junction and the output conductance to increase due to the time-dependent net negative charge concentration in the semi-insulating substrate as a result of self-backgating with the applied signal frequency. This model has been incorporated in PSPICE and includes a time-dependent I-V curve model, a capacitance model, an RC network describing the effective substrate- induced capacitance and resistance, and a switching resistance providing device symmetry. An analytical capacitance model describes the dependence of capacitance on V/sub gs/ and V/sub ds/ and includes the channel-substrate junction modulation by the self-backgating effect. A transit- time delay is also included in the transconductances, g/sub m/ and g/sub mbs/, for model accuracy and to describe the phase shift of S-parameters. Measured data correspond to simulations by this model of the low-frequency anomalous characteristics, voltage-dependent capacitances, and S- parameters of conventional GaAs MESFETs for linear and microwave circuit design (19 Refs.) DESCRIPTORS: gallium arsenide; III-V semiconductors; Schottky gate field effect transistors; semiconductor device models; solid-state microwave devices IDENTIFIERS: semiconductors; deep level traps; substrate induced resistance; self backgating MESFET model; low-frequency anomalies; deep-level trap effects; transconductance reduction; electron emission; EL2; depletion width change; Schottky gate junction; output conductance; time-dependent net negative charge concentration; semi-insulating substrate; PSPICE; time-dependent I-V curve model; capacitance model; RC network; effective substrate-induced capacitance; switching resistance; device symmetry; analytical capacitance model; dependence of capacitance; channel-substrate junction modulation; self-backgating effect; transit-time delay; phase shift of S-parameters; voltage-dependent capacitances; S-parameters; GaAs CLASS CODES: B1350F (Solid-state circuits and devices); B2520D (II-VI and III-V semiconductors); B2560S (Other field effect devices); B2560B (Modelling and equivalent circuits)