[Databa[Search[Result[RECORD[News][Exit] [Help] [ Database= Inspec | Search=au=("forbes | Results= 81 records | Records= 21, leonard") or 22, au=("forbes 23, l") 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40 ] --------------------------------------------------------------------------- [Email Records] --------------------------------------------------------------------------- Record: 21 RECORD NO.: 3787452 INSPEC Abstract No: B91002135 AUTHOR: Lee, M.; Forbes, L.; Hallen, T.; Tuinenega, P. CORP SOURCE: Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA TITLE: An analytical self-backgating GaAs MESFET model including deep-level trap effects SOURCE: International Electron Devices Meeting 1989. Technical Digest (Cat. No.89CH2637-7), p. 913, 315-18 PLACE OF PUBL: USA LANGUAGE: English PUBLISHER: IEEE; New York, NY, USA SPONSOR ORG: IEEE CONF LOCATION: Washington, DC, USA; 3-6 Dec. 1989 YEAR: 1989 COPYRIGHT NO: CH2637-7/89/0000-0315$01.00 TREATMENT: T Theoretical or Mathematical ABSTRACT: A self-backgating GaAs MESFET model which can simulate low- frequency anomalies has been developed by including deep- level trap effects which cause reduction of the transconductance and increase of the output conductance and the saturation drain current with the applied signal frequency. This model has been incorporated into PSPICE and includes a time-dependent I-V curve model, a capacitance model, a RC network describing the effective substrate induced capacitance and resistance, and a switching resistance providing device symmetry. An analytical capacitance model describes the dependence of capacitance on V/sub gs/ and V/sub ds/ and also includes the channel- substrate junction modulation by the self-backgating effect. Measured data correspond to simulations by this model of the low-frequency anomalous characteristics, voltage-dependent capacitances, and S-parameters of conventional GaAs MESFETs for linear and microwave circuit design (8 Refs.) DESCRIPTORS: deep levels; gallium arsenide; III-V semiconductors; S- parameters; Schottky gate field effect transistors; semiconductor device models IDENTIFIERS: semiconductors; analytical model; deep-level trap effects; self-backgating GaAs MESFET model; simulate low-frequency anomalies; transconductance; output conductance; saturation drain current; signal frequency; incorporated into PSPICE; time-dependent I-V curve model; capacitance model; RC network; effective substrate induced capacitance; resistance; switching resistance; analytical capacitance model; channel-substrate junction modulation; self- backgating effect; low-frequency anomalous characteristics; voltage-dependent capacitances; S-parameters; GaAs MESFETs; microwave circuit design CLASS CODES: B2560S (Other field effect devices); B2520D (II-VI and III-V semiconductors); B2560B (Modelling and equivalent circuits) --------------------------------------------------------------------------- Record: 22 RECORD NO.: 3515215 INSPEC Abstract No: A90007931 AUTHOR: Godbole, H.; Haddad, H.; Forbes, L. CORP SOURCE: Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA TITLE: An investigation of bulk stacking faults in silicon using photocapacitance transient spectroscopy SOURCE: Materials Letters, vol.8, no.6-7, p. 201-3 ISSN: 0167-577X CODEN: MLETDJ PLACE OF PUBL: Netherlands LANGUAGE: English YEAR: July 1989 COPYRIGHT NO: 0167-577X/89/$03.50 TREATMENT: X Experimental ABSTRACT: Two-step heat-treated silicon wafers have been used to determine the electrical activity of bulk stacking faults. DLTS measurements by Forbes and Haddad show a dominant energy level at E/sub c/-E/sub t/=0.48+or-0.05 eV due to oxygen-induced stacking faults. These wafers have been processed in two different facilities to minimize the possibility that the results might depend on impurities incorporated during wafer processing. Low-temperature photocapacitance transient spectroscopy (PCTS) was used to study the optical cross section as a function of incident photon energies, in the 1300 to 3000 nm range. PCTS measurements done on the same samples show a dominant level at E/sub c/-E/sub t/=0.48+or-0.05 eV. These results are in excellent correlation with the DLTS measurements (8 Refs.) DESCRIPTORS: deep level transient spectroscopy; elemental semiconductors; silicon; stacking faults IDENTIFIERS: semiconductor; bulk stacking faults; photocapacitance transient spectroscopy; electrical activity; energy level; optical cross section; PCTS; Si CLASS CODES: A6170P (Stacking faults, stacking fault tetrahedra and other planar or extended defects); A7155F (Tetrahedrally bonded nonmetals) --------------------------------------------------------------------------- Record: 23 RECORD NO.: 3280067 INSPEC Abstract No: A89013887 AUTHOR: Haddad, H.; Forbes, L. CORP SOURCE: Hewlett-Packard Northwest Integrated Circuits Div., Corvallis, OR, USA TITLE: Electrical activity of bulk stacking faults in silicon SOURCE: Materials Letters, vol.7, no.3, p. 99-101 ISSN: 0167-577X CODEN: MLETDJ PLACE OF PUBL: Netherlands LANGUAGE: English YEAR: Sept. 1988 COPYRIGHT NO: 0167-577X/88/$03.50 TREATMENT: X Experimental ABSTRACT: Two-step heat-treated silicon wafers have been used to determine the electrical activity of bulk stacking faults. These wafers have been processed in two different facilities to minimize the possibility that the results might depend on impurities incorporated during wafer processing. DLTS measurements show a dominant energy level at E/sub c/-E/sub t/=0.48+or-0.05 eV due to oxygen-induced stacking faults. Trap concentrations have been correlated to optically detectable bulk stacking faults when the size of the stacking faults is more than 1 mu m. The results show the size and density of the stacking faults are related to the observed electrical activity of the microdefects (10 Refs.) DESCRIPTORS: deep level transient spectroscopy; defect electron energy states; elemental semiconductors; silicon; stacking faults IDENTIFIERS: semiconductor; stacking faults; electrical activity; DLTS; microdefects; Si CLASS CODES: A7155F (Tetrahedrally bonded nonmetals) --------------------------------------------------------------------------- Record: 24 RECORD NO.: 3157580 INSPEC Abstract No: B88039739 AUTHOR: Canfield, P.C.; Medinger, J.; Allstot, D.J.; Forbes, L.; McCamant, A.J.; Vetanen, B.A.; Odekirk, B.; Finchem, E.P.; Gleason, K.R. CORP SOURCE: Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA TITLE: High speed quarter micron buried-channel MESFETs with improved output characteristics for analog applications SOURCE: Proceedings IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits (Cat. No.87CH2526-2), p. vi+399, 247-54 PLACE OF PUBL: USA TRANSLATED IN: B02 LANGUAGE: English PUBLISHER: IEEE; New York, NY, USA SPONSOR ORG: IEEE CONF LOCATION: Ithaca, NY, USA; 10-12 Aug. 1987 YEAR: 1987 COPYRIGHT NO: CH2526-2/87/0000-0247$01.00 TREATMENT: A Application; P Practical ABSTRACT: Precision analog circuits depend critically on consistent and matched small-signal parameter values for proper function and feasible design. Buried-channel MESFETs, which have been shown to offer significant improvements in the behaviour of the small-signal parameters g/sub m/ and g/sub ds/, are discussed. These major improvements increase the potential for enhanced performance of analog circuits ind increase the potential for successful implementation of analog ICs for data acquisition and other precision applications. In addition, the reduction of short-channel effects by the buried-channel structure has made possible the implementation of quarter-micron-gate length devices with high bandwidth. These improvements have all been achieved with fabrication methods currently in use in most GaAs manufacturing facilities. These improvements will significantly extend the application base of GaAs ICs without incurring the increased complexities of advanced heteroepitaxial devices (9 Refs.) DESCRIPTORS: field effect integrated circuits; gallium arsenide; III-V semiconductors; linear integrated circuits; Schottky gate field effect transistors IDENTIFIERS: high-speed devices; III-V semiconductors; buried-channel MESFETs; analog applications; small-signal parameters; analog ICs; quarter-micron-gate length; 0.25 micron; GaAs CLASS CODES: B2560S (Other field effect devices); B2570H (Other field effect integrated circuits) --------------------------------------------------------------------------- Record: 25 RECORD NO.: 3152266 INSPEC Abstract No: A88080782; B88039153 AUTHOR: Aminzadeh, M.; Forbes, L. CORP SOURCE: Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA TITLE: Recombination lifetime of short-base-width devices using the pulsed MOS capacitor technique SOURCE: IEEE Transactions on Electron Devices, vol.35, no.4, pt.1, p. 518-21 ISSN: 0018-9383 CODEN: IETDAI PLACE OF PUBL: USA TRANSLATED IN: A18 LANGUAGE: English YEAR: April 1988 COPYRIGHT NO: 0018-9383/88/0400-0518$01.00 TREATMENT: T Theoretical or Mathematical ABSTRACT: The authors point out that the technique of D.K. Schroder, J.D. Whitfield, and C.J. Varker (see ibid., vol.ED-31, no.4, p.462, 1984) for the determination of recombination lifetime using pulsed MOS capacitors at elevated temperatures does not consider lateral quasi-neutral bulk generation and the time dependence of the width of the space-charge region in short-base-width devices (i.e. epitaxial wafers). Consequently, calculations using this technique indicate that the recombination lifetime is a function of device diameter. A simple one-dimensional approach is proposed in which bulk generation in the lateral area of the device is taken into consideration resulting in a fairly uniform recombination lifetime that is independent of the device diameter for short-base-width devices (5 Refs.) DESCRIPTORS: capacitors; carrier lifetime; metal-insulator-semiconductor structures; semiconductor device models IDENTIFIERS: short-base-width devices; pulsed MOS capacitor technique; determination of recombination lifetime; elevated temperatures; epitaxial wafers; one-dimensional approach; bulk generation CLASS CODES: A7220J (Charge carriers: generation, recombination, lifetime, and trapping); A7340Q (Metal-insulator- semiconductor structures); B2130 (Capacitors); B2520 (Semiconductor theory, materials and properties); B2530F (Metal-insulator-semiconductor structures); B2560B (Modelling and equivalent circuits) --------------------------------------------------------------------------- Record: 26 RECORD NO.: 3097884 INSPEC Abstract No: B88020008 AUTHOR: Canfield, P.C.; Allstot, D.J.; Medinger, J.; Forbes, L.; McCamant, A.J.; Vetanen, W.A.; Odekirk, B.; Finchem, E.P.; Gleason, K.R. CORP SOURCE: Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA TITLE: Buried-channel GaAs MESFETs with improved small-signal characteristics SOURCE: GaAs IC Symposium: IEEE Gallium Arsenide Integrated Circuit Symposium. Technical Digest 1987 (Cat. No.87CH2506-4), p. 276, 163-6 PLACE OF PUBL: USA TRANSLATED IN: B12 LANGUAGE: English PUBLISHER: IEEE; New York, NY, USA SPONSOR ORG: IEEE CONF LOCATION: Portland, OR, USA; 13-16 Oct. 1987 YEAR: 1987 COPYRIGHT NO: CH2506-4/87/0000-0163$01.00 TREATMENT: P Practical ABSTRACT: Buried-channel GaAs MESFETs with 0.25- mu m gate lengths have been fabricated by ion implantation into undoped LEC material. Compared to conventional 0.5- mu m and 1- mu m MESFETs, these devices exhibit higher gain, wider bandwidth, reduced short-channel effects, and much less dispersion and frequency dependence of the small-signal parameter values. These improvements are obtained because the carrier trapping at the channel-substrate and channel-surface interfaces, common in conventional MESFETS, is considerably reduced in the buried-channel MESFET by the presence of the implanted p- type layers (7 Refs.) DESCRIPTORS: gallium arsenide; III-V semiconductors; ion implantation; Schottky gate field effect transistors; solid-state microwave devices IDENTIFIERS: channel-substrate interface; gain improvement; buried channel devices; III-V semiconductors; microwave operation; submicron gate length; bandwidth improvement; MESFETs; small- signal characteristics; ion implantation; undoped LEC material; short-channel effects; carrier trapping; channel- surface interfaces; implanted p-type layers; 0.25 micron; GaAs CLASS CODES: B1350F (Solid-state circuits and devices); B2560S (Other field effect devices) --------------------------------------------------------------------------- Record: 27 RECORD NO.: 3097853 INSPEC Abstract No: B88019103 AUTHOR: Anderson, W.T.; Simons, M.; Forbes, L.; Koyama, R.Y.; Reeder, T.M. CORP SOURCE: US Naval Res. Lab., Washington, DC, USA TITLE: Transient radiation upset of GaAs buffered FET logic ICs SOURCE: GaAs IC Symposium: IEEE Gallium Arsenide Integrated Circuit Symposium. Technical Digest 1987 (Cat. No.87CH2506-4), p. 276, 23-6 PLACE OF PUBL: USA TRANSLATED IN: A06 LANGUAGE: English PUBLISHER: IEEE; New York, NY, USA SPONSOR ORG: IEEE CONF LOCATION: Portland, OR, USA; 13-16 Oct. 1987 YEAR: 1987 COPYRIGHT NO: CH2506-4/87/0000-0023$01.00 TREATMENT: X Experimental ABSTRACT: Transient radiation effects were studied in a number of GaAs buffered FET logic (BFL) ICs including ripple counters, NOR gates, and ring oscillators. The hardness level was found to depend more on the dose per pulse than on dose rate; the apparent hardness level increases with increasing dose rate. Depending on the circuit, upset resulted from changes in circuit bias resulting from large FET photocurrents, induced oscillations during the photocurrent, and long-term FET currents resulting from charge trapped in the substrate. Electron and hole trapping levels were determined by measuring the temperature dependence of the long-term current transients (11 Refs.) DESCRIPTORS: field effect integrated circuits; gallium arsenide; III-V semiconductors; integrated logic circuits; radiation hardening (electronics) IDENTIFIERS: semiconductors; transient radiation upset; radiation hardening; electron trapping; buffered FET logic; BFL; ripple counters; NOR gates; ring oscillators; hardness level; dose per pulse; dose rate; large FET photocurrents; induced oscillations; long-term FET currents; hole trapping; temperature dependence; long-term current transients; GaAs CLASS CODES: B1265B (Logic circuits); B2520D (II-VI and III-V semiconductors); B2570H (Other field effect integrated circuits) --------------------------------------------------------------------------- Record: 28 RECORD NO.: 3090117 INSPEC Abstract No: B88019938 AUTHOR: Canfield, P.; Forbes, L. CORP SOURCE: Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA TITLE: Lateral n-p-n bipolar transistors by ion implantation into semi-insulating GaAs SOURCE: Solid-State Electronics, vol.31, no.1, p. 123-5 ISSN: 0038-1101 CODEN: SSELA5 PLACE OF PUBL: UK TRANSLATED IN: A19 LANGUAGE: English YEAR: Jan. 1988 COPYRIGHT NO: 0038-1101/88/$3.00+0.00 TREATMENT: P Practical; X Experimental ABSTRACT: Lateral bipolars do not require steps or deep contacts to make contact with the subcollector or highly doped very thin epilayers for the base region and they can draw upon the semi-insulating properties of the GaAs substrates for device isolation. The n/sup +/ emitter and collector regions were formed by a 5*10/sup 13/ cm/sup -2/, 180 KeV Si/sup +/ implant into high purity LEC substrates. The p-type base region was formed by a double implant of Be and a single implant of Si. This results in a p/sup -/ base layer with improved minority carrier lifetimes and a reduction in surface recombination due to the presence of the highly doped p-type layer at the surface (5 Refs.) DESCRIPTORS: bipolar transistors; gallium arsenide; III-V semiconductors; ion implantation IDENTIFIERS: lateral n-p-n bipolar transistors; ion implantation; semi- insulating properties; LEC substrates; minority carrier lifetimes; surface recombination; GaAs; GaAs CLASS CODES: B2550B (Semiconductor doping); B2560J (Bipolar transistors) --------------------------------------------------------------------------- Record: 29 RECORD NO.: 3086013 INSPEC Abstract No: A88039355 AUTHOR: Wijaranakula, W.; Matlock, J.H.; Mollenkopf, H.; Burke, P.; Forbes, L. CORP SOURCE: SEH America, Inc., Mater. Characterization Lab., Vancouver, WA, USA TITLE: Oxygen precipitation in p/p+(100) epitaxial silicon material SOURCE: Journal of the Electrochemical Society, vol.134, no.9, p. 2310-16 ISSN: 0013-4651 CODEN: JESOAN PLACE OF PUBL: USA TRANSLATED IN: C03 LANGUAGE: English YEAR: Sept. 1987 TREATMENT: X Experimental ABSTRACT: Substrate and epitaxial silicon wafers from silicon crystals containing oxygen concentrations ranging between 25 and 32 ppma were heat-treated using one- and two-step heat- treatment processes. An epitaxial deposition thermal simulation heat-treatment was also applied to the substrate wafers. The results indicate that a significant amount of preexisting microprecipitates are annihilated during the epitaxial deposition process, and the thermal history, as well as the growth conditions of the crystal, play an important role in the oxygen precipitation process. It is proposed that during epitaxial deposition, preexisting microprecipitates are dissolved by out-diffusion of oxygen atoms from the precipitate particles as well as by the generation of excess self-interstitials at the growing epitaxial surface, which results in retardation of the oxygen precipitation process (28 Refs.) DESCRIPTORS: elemental semiconductors; epitaxial growth; heat treatment; impurities; oxygen; precipitation; silicon IDENTIFIERS: semiconductor; heat-treatment; epitaxial deposition; microprecipitates; growth conditions; Si:O CLASS CODES: A6480G (Microstructure); A6855 (Thin film growth, structure, and epitaxy) --------------------------------------------------------------------------- Record: 30 RECORD NO.: 2901097 INSPEC Abstract No: B87038268 AUTHOR: Canfield, P.; Forbes, L. CORP SOURCE: Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA TITLE: Buried-channel GaAs MESFETs with immunity to ionizing optical radiation effects SOURCE: IEEE Electron Device Letters, vol.EDL-8, no.3, p. 113-15 ISSN: 0741-3106 CODEN: EDLEDZ PLACE OF PUBL: USA TRANSLATED IN: A11 LANGUAGE: English YEAR: March 1987 COPYRIGHT NO: 0741-3106/87/0300-0113$01.00 TREATMENT: X Experimental ABSTRACT: The effects of high-intensity visible light on various GaAs MESFET structures are examined and compared. The buried- channel MESFETs were found to be insensitive to ionizing radiation both in terms of increases of the drain current due to photocurrents and in terms of long-term transients due to charging of deep levels as is found in standard FETs. These results indicate that the buried-channel MESFETS should be significantly more immune to transient radiation effects in severe radiation environments (9 Refs.) DESCRIPTORS: gallium arsenide; III-V semiconductors; radiation effects; Schottky gate field effect transistors; transients IDENTIFIERS: deep level charging; drain current; ionizing optical radiation effects; high-intensity visible light; buried- channel MESFETs; long-term transients; severe radiation environments; GaAs CLASS CODES: B2560S (Other field effect devices) --------------------------------------------------------------------------- Record: 31 RECORD NO.: 2901088 INSPEC Abstract No: B87038265 AUTHOR: Canfield, P.; Medinger, J.; Forbes, L. CORP SOURCE: Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA TITLE: Buried-channel GaAs MESFETs with frequency-independent output conductance SOURCE: IEEE Electron Device Letters, vol.EDL-8, no.3, p. 88-9 ISSN: 0741-3106 CODEN: EDLEDZ PLACE OF PUBL: USA TRANSLATED IN: A02 LANGUAGE: English YEAR: March 1987 COPYRIGHT NO: 0741-3106/87/0300-0088$01.00 TREATMENT: X Experimental ABSTRACT: The output conductance of GaAs MESFETS is shown to be a function of frequency and to have a well-defined temperature dependence. This behavior is in agreement with other reports of the behavior of GaAs ion-implanted MESFETs. The output conductance of buried-channel GaAs MESFETs is shown to be independent of frequency and temperature. This is an important improvement in the output characteristics with many implications for GaAs analog and digital circuits (5 Refs.) DESCRIPTORS: gallium arsenide; III-V semiconductors; Schottky gate field effect transistors IDENTIFIERS: buried channel MESFETs; frequency-independent output conductance; temperature dependence; output characteristics; GaAs CLASS CODES: B2560S (Other field effect devices) --------------------------------------------------------------------------- Record: 32 RECORD NO.: 2900322 INSPEC Abstract No: B87038293; C87036011 AUTHOR: Forbes, L.; Rastegar, B. CORP SOURCE: Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA TITLE: A desktop-computer-based calculation of high-frequency MOS C- V curves SOURCE: IEEE Transactions on Electron Devices, vol.ED-34, no.2, pt.1, p. 427-32 ISSN: 0018-9383 CODEN: IETDAI PLACE OF PUBL: USA TRANSLATED IN: B15 LANGUAGE: English YEAR: Feb. 1987 COPYRIGHT NO: 0018-9383/87/0200-0427$01.00 TREATMENT: T Theoretical or Mathematical ABSTRACT: A simple desktop-computer-based technique for the calculation of the C-V (capacitance-voltage) curves of MOS capacitors is presented. The equivalent circuit model for low- and high-frequency semiconductor capacitance and, in the latter case, both with and without minority carriers, has been investigated. The computer simulation of the equivalent circuit model revealed that the C-V curves for both the exact high frequency and the high frequency with minority carriers are essentially the same. A calculation of the low-frequency C-V curve has been performed and plotted for a direct comparison with the computer simulation by the equivalent circuit model. Application of this technique will allow both high-frequency MOS C-V measurements and calculated theoretical high-frequency C-V curves to be displayed and plotted on the desktop computer system(s). A complete model for each case and an explanation of programming steps are included (12 Refs.) DESCRIPTORS: capacitors; electronic engineering computing; equivalent circuits; metal-insulator-semiconductor devices; minority carriers; semiconductor device models IDENTIFIERS: HF capacitance-voltage curves; C-V measurements; metal-oxide- semiconductor device; desktop-computer-based calculation; MOS capacitors; equivalent circuit model; high-frequency semiconductor capacitance; minority carriers; computer simulation CLASS CODES: B2560B (Modelling and equivalent circuits); B2560S (Other field effect devices); C7410D (Electronic engineering) --------------------------------------------------------------------------- Record: 33 RECORD NO.: 2848177 INSPEC Abstract No: A87045060 AUTHOR: Wijaranakula, W.; Burke, P.M.; Forbes, L.; Matlock, J.H. CORP SOURCE: Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA TITLE: Effect of pre- and postepitaxial deposition annealing on oxygen precipitation in silicon SOURCE: Journal of Materials Research, vol.1, no.5, p. 698-704 ISSN: 0884-2914 CODEN: JMREEE PLACE OF PUBL: USA TRANSLATED IN: A11 LANGUAGE: English YEAR: Sept.-Oct. 1986 COPYRIGHT NO: 0884-2914/86/050698-07$01.75 TREATMENT: X Experimental ABSTRACT: Substrate material used for fabrication of P/P+epitaxial silicon wafers was preannealed at 650 degrees C in nitrogen ambient prior to the epitaxial deposition process for various times up to 300 min. The substrate material originated from a characterized crystal ingot. The results show that annealing before epitaxial deposition can preserve oxide precipitate nuclei from dissolution during the epitaxial deposition process. Additional postepitaxial annealing at 750 degrees C further enhances the growth of bulk defects (13 Refs.) DESCRIPTORS: annealing; boron; elemental semiconductors; epitaxial growth; oxygen; precipitation; semiconductor epitaxial layers; semiconductor growth; silicon IDENTIFIERS: semiconductors; annealing; precipitation; epitaxial deposition; Si:B,O CLASS CODES: A6475 (Solubility, segregation, and mixing); A6855 (Thin film growth, structure, and epitaxy); A8140G (Other heat and thermomechanical treatments) --------------------------------------------------------------------------- Record: 34 RECORD NO.: 2848176 INSPEC Abstract No: A87045059 AUTHOR: Wijaranakula, W.; Burke, P.M.; Forbes, L. CORP SOURCE: Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA TITLE: Internal gettering heat treatments and oxygen precipitation in epitaxial silicon wafers SOURCE: Journal of Materials Research, vol.1, no.5, p. 693-7 ISSN: 0884-2914 CODEN: JMREEE PLACE OF PUBL: USA TRANSLATED IN: A10 LANGUAGE: English YEAR: Sept.-Oct. 1986 COPYRIGHT NO: 0884-2914/86/050693-05$01.75 TREATMENT: X Experimental ABSTRACT: As-received P/P+(100) epitaxial silicon wafers were heat treated using the one-, two-, and three-step internal gettering heat treatment cycles in wet oxygen, dry oxygen, and nitrogen ambients. The results indicate that ambients have an effect on the growth of bulk defects and denuded zone formation in the epitaxial silicon wafers (10 Refs.) DESCRIPTORS: boron; elemental semiconductors; heat treatment; oxygen; precipitation; semiconductor epitaxial layers; silicon IDENTIFIERS: semiconductors; epitaxial wafers; bulk defects growth; internal gettering heat treatment; denuded zone formation; Si:B,O CLASS CODES: A6475 (Solubility, segregation, and mixing); A6855 (Thin film growth, structure, and epitaxy); A8140G (Other heat and thermomechanical treatments) --------------------------------------------------------------------------- Record: 35 RECORD NO.: 2844152 INSPEC Abstract No: A87038219; B87017703 AUTHOR: Wijaranakula, W.; Burke, P.; Forbes, L.; Matlock, J.H. EDITOR: Wittmer, M.; Stimmell, J.; Strathman, M. CORP SOURCE: Oregon State Univ., Corvallis, OR, USA TITLE: Effect of preanneal heat treatment on oxygen precipitation in epitaxial silicon SOURCE: Materials Issues in Silicon Integrated Circuit Processing Symposium, p. xvii+535, 139-44 PLACE OF PUBL: USA TRANSLATED IN: B01 ISBN: 0931837375 LANGUAGE: English PUBLISHER: Mater. Res. Soc; Pittsburgh, PA, USA SPONSOR ORG: Mater. Res. Soc CONF LOCATION: Palo Alto, CA, USA; 15-18 April 1986 YEAR: 1986 TREATMENT: X Experimental ABSTRACT: Substrate wafers used for fabrication of P/P+ epitaxial silicon wafers were preanneal heat treated at 650 degrees C in nitrogen ambients prior to the epitaxial deposition process for various periods up to 300 minutes. Subsequently, epitaxial wafers were subjected to CMOS simulation heat treatments. Postepitaxial nucleation heat treatment at 750 degrees C in nitrogen ambient was also done on some epitaxial wafers. The results shows that preanneal heat treatment can preserve precipitate nuclei from dissolution during the epitaxial deposition process and lead to a high bulk defect density. These results also indicate the effect of the thermal history and spatial location in the grown crystal on the bulk defect formation (7 Refs.) DESCRIPTORS: elemental semiconductors; heat treatment; oxygen; precipitation; semiconductor epitaxial layers; silicon IDENTIFIERS: postepitaxial nucleation heat treatment; preanneal heat treatment; precipitation; epitaxial deposition; epitaxial wafers; CMOS simulation heat treatments; defect density; bulk defect formation; Si:O wafers; N/sub 2/ ambient CLASS CODES: A6475 (Solubility, segregation, and mixing); A6855 (Thin film growth, structure, and epitaxy); B2520C (Elemental semiconductors) --------------------------------------------------------------------------- Record: 36 RECORD NO.: 2844140 INSPEC Abstract No: B87017897 AUTHOR: Aminzadeh, M.; Forbes, L. EDITOR: Wittmer, M.; Stimmell, J.; Strathman, M. CORP SOURCE: Dept. of Electr. Eng., Oregon State Univ., Corvallis, OR, USA TITLE: Fast Zerbst transient analysis and application to intrinsic gettered p-type epitaxial wafers SOURCE: Materials Issues in Silicon Integrated Circuit Processing Symposium, p. xvii+535, 59-64 PLACE OF PUBL: USA TRANSLATED IN: A09 ISBN: 0931837375 LANGUAGE: English PUBLISHER: Mater. Res. Soc; Pittsburgh, PA, USA SPONSOR ORG: Mater. Res. Soc CONF LOCATION: Palo Alto, CA, USA; 15-18 April 1986 YEAR: 1986 TREATMENT: A Application ABSTRACT: One of the principal difficulties in applying the Zerbst analysis to MOS capacitor transient recovery is the extremely long retention time of the MOS capacitor in high lifetime materials. Typically the retention time is thousands of seconds at room temperature, so long times are required for a significant number of measurements. Furthermore, extrapolating the result of high temperature measurements back to room temperature can lead to large errors. A modified C-t transient response using a step from accumulation to depletion followed by light and then a small step from inversion to stronger inversion speeds up the generation lifetime measurement and separates the surface generation from the bulk generation. Pre- and post-epitaxial intrinsically gettered p/p/sup +/ wafers were subjected to high temperature CMOS process simulation and MOS capacitors with Al dots and guard rings were fabricated. Generation lifetime of about 5 msec were measured using the modified fast Zerbst method on properly intrinsically gettered epitaxial wafers, particularly the pre-epitaxial intrinsically gettered wafers (7 Refs.) DESCRIPTORS: carrier lifetime; getters; integrated circuit technology; metal-insulator-semiconductor structures; semiconductor epitaxial layers; semiconductor technology; transients IDENTIFIERS: Zerbst transient analysis; intrinsic gettered p-type epitaxial wafers; MOS capacitor transient recovery; retention time; accumulation; depletion; inversion; generation lifetime measurement; surface generation; bulk generation; CMOS process simulation; Al-SiO/sub 2/-Si CLASS CODES: B2530F (Metal-insulator-semiconductor structures); B2550 (Semiconductor device technology); B2570D (CMOS integrated circuits) --------------------------------------------------------------------------- Record: 37 RECORD NO.: 2844139 INSPEC Abstract No: A87038511 AUTHOR: Whitwer, F.D.; Haddad, H.; Forbes, L. EDITOR: Wittmer, M.; Stimmell, J.; Strathman, M. CORP SOURCE: Dept. of Electr. Eng., Oregon State Univ., Corvallis, OR, USA TITLE: DLTS characterization of precipitation induced microdefects SOURCE: Materials Issues in Silicon Integrated Circuit Processing Symposium, p. xvii+535, 53-7 PLACE OF PUBL: USA TRANSLATED IN: A08 ISBN: 0931837375 LANGUAGE: English PUBLISHER: Mater. Res. Soc; Pittsburgh, PA, USA SPONSOR ORG: Mater. Res. Soc CONF LOCATION: Palo Alto, CA, USA; 15-18 April 1986 YEAR: 1986 TREATMENT: X Experimental ABSTRACT: Capacitance DLTS measurements have been performed on heavily precipitated n- and p-type silicon wafers. The results indicate heavy metal gettering with a mid-bandgap deep level (0.55 eV) for n-type silicon. The results for p-type silicon show a band of states present in the lower half of the bandgap. This band of states correlates well to the band of allowed energies found in heavily dislocated p-type silicon (7 Refs.) DESCRIPTORS: deep level transient spectroscopy; defect electron energy states; elemental semiconductors; precipitation; silicon IDENTIFIERS: n-type wafers; p-type wafers; semiconductor; precipitation induced microdefects; DLTS; heavy metal gettering; deep level; band of states; Si CLASS CODES: A6475 (Solubility, segregation, and mixing); A7155F (Tetrahedrally bonded nonmetals) --------------------------------------------------------------------------- Record: 38 RECORD NO.: 2754511 INSPEC Abstract No: B86063308 AUTHOR: Canfield, P.C.; Forbes, L. CORP SOURCE: Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA TITLE: Suppression of drain conductance transients, drain current oscillations, and low-frequency generation-recombination noise in GaAs FETs using buried channels SOURCE: IEEE Transactions on Electron Devices, vol.ED-33, no.7, p. 925-8 ISSN: 0018-9383 CODEN: IETDAI PLACE OF PUBL: USA TRANSLATED IN: A08 LANGUAGE: English YEAR: July 1986 COPYRIGHT NO: 0018-9383/86/07000-0925$01.00 TREATMENT: X Experimental ABSTRACT: The drain conductance transients of buried-channel MESFETs fabricated on GaAs are compared with conductance transients of regular MESFETs;. The buried-channel MESFETs are shown to be essentially free of drain transients in comparison to the regularly fabricated MESFETs. In addition, the buried- channel FETs are shown to be free of oscillations in the drain current, which have been found in FETs manufactured by common techniques (26 Refs.) DESCRIPTORS: electron device noise; gallium arsenide; III-V semiconductors; random noise; Schottky gate field effect transistors; transients IDENTIFIERS: GaAs MESFET; drain conductance transients; drain current oscillations; generation-recombination noise; buried channels CLASS CODES: B2560S (Other field effect devices) --------------------------------------------------------------------------- Record: 39 RECORD NO.: 2658530 INSPEC Abstract No: B86028523 AUTHOR: Forbes, L.; Whitwer, F.D.; Peng, J.D. EDITOR: Fair, R.B.; Pearce, C.W.; Washburn, J. CORP SOURCE: Dept. of Electr. Eng., Oregon State Univ., Corvallis, OR, USA TITLE: Oxygen precipitation in CMOS wafers SOURCE: Impurity Diffusion and Gettering in Silicon Symposium, p. xiii+284, 257-62 PLACE OF PUBL: USA TRANSLATED IN: B13 ISBN: 0931837014 LANGUAGE: English PUBLISHER: Mater. Res. Soc; Pittsburgh, PA, USA SPONSOR ORG: Mater. Res. Soc CONF LOCATION: Boston, MA, USA; 27-30 Nov. 1984 YEAR: 1985 TREATMENT: P Practical; X Experimental ABSTRACT: The application of denuding, nucleation, and intrinsic gettering in CMOS integrated circuit processes is described. Specifically, it will be demonstrated that an initial oxidizing step, as many manufacturers are using, seriously retards the effectiveness of any subsequent nucleation step or procedure. The results of a large number of one-step, two- step, and three-step heat treatments are summarized and design criteria for controlled oxygen precipitation in integrated circuit fabrication are described. Two-step heat treatments, without denuding and with the nucleation step first, have been used to induce precipitates close to the surface of CMOS wafers and DLTS measurements made to deduce the effectiveness of intrinsic gettering and the electrical characteristics of precipitation induced microdefects (6 Refs.) DESCRIPTORS: CMOS integrated circuits; getters; heat treatment; integrated circuit technology; nucleation; precipitation IDENTIFIERS: O precipitation; denuding; nucleation; intrinsic gettering; CMOS integrated circuit processes; heat treatments; design criteria; integrated circuit fabrication; electrical characteristics; precipitation induced microdefects CLASS CODES: B2570D (CMOS integrated circuits) --------------------------------------------------------------------------- Record: 40 RECORD NO.: 2576653 INSPEC Abstract No: B86002195 AUTHOR: Forbes, L.; Canfield, P.; Gleason, R.; McCamant, A. EDITOR: Look, D.C.; Blakemore, J.S. CORP SOURCE: Oregon State Univ., Corvallis, OR, USA TITLE: Low frequency noise in GaAs FETs SOURCE: Semi-Insulating III-V materials, p. xiii+504, 392-6 PLACE OF PUBL: UK TRANSLATED IN: C02 ISBN: 1850140316 LANGUAGE: English PUBLISHER: Shiva Publishing; Nantwich, UK SPONSOR ORG: IEEE CONF LOCATION: Kah-nee-ta, OR, USA; 24-26 April 1984 YEAR: 1984 TREATMENT: X Experimental ABSTRACT: A survey has been made of low frequency noise in different types of GaAs FET structures. A major component of the noise in GaAs JFETs is shown to be generation-recombination, which can be correlated to conductance transients measured on the same devices. Measurements at high temperatures, however, show that all devices have a residual 1/f noise component which cannot be attributed to generation-recombination and/or trapping (6 Refs.) DESCRIPTORS: electron device noise; electron-hole recombination; gallium arsenide; III-V semiconductors; junction gate field effect transistors; random noise IDENTIFIERS: JFET; junction gate field effect transistor; semiconductor; residual 1/f noise; low frequency noise; GaAs FET structures; generation-recombination; conductance transients; trapping CLASS CODES: B2560S (Other field effect devices)